HW 6
HW 6
Homework 6
Due May 13, 2015
Note: Prepare for your final exam. I will let you know if you have an A next Wednesday. The Final
is on Wednesday from 10:30AM to 12:45PM. The room will be announced on Blackboard.
(20pts) Problem 1:
Consider the following MIPS code:
add $t3,$t2,$t1
lw $t4,0($t3)
sw $t7,0($t3)
add $t6,$t2,$t8
addi $t3,$t5,4
(a) Provide pipeline diagram from CC1 to CC5 with respect to time for all of the instructions.
(b) Can you identify the type of hazard in pipeline for executing the code?
(c) What is the solution to the hazard? If NOP (noop or bubbles) have to be inserted to avoid
hazard, where will you put them?
(d) Put the code into the MIPS simulator and observe your findings. You may want to load your
own numbers into the registers to see better register contents. (a) Provide contents of
registers by printing or using screen print to demonstrate the contents after each instruction
execution. (b) Provide your .asm file.
Problem 2: MIPS code compilation
Write a MIPS program to find the sum of all prime numbers from 0 to 10. Follow the steps below.
1. Simulate the program using QtSpim.
2. Initialize an array to store the prime numbers 2,3,5, and 7.
3. Use variable declarations using the following:
Size: .word 4
#array size
Array: .word 2,3,5,7 #array elements
Sum: .word 0
#sum
4. Load word (lw) size to $s0
5. Load address (la) of the array into register $t0
6. Begin loop
7. Load word first array content into register $t1
8. Add content of register $t1 with register $s1
9. Increment register $t0 to the address of second array element
10. Note: Array address increments by 4.
11. Decrement register $s0
12. If $s0 is not zero, goto step 6.
13. Store word (sw) data from sum into register $s1
Provide the following (no hand written code):
(a) (10 pts) Provide print screen shot of your .asm file.
(b) (20 pts) Provide print screen shot of the QtSpim showing register $s1=11.
(20 pts) Problem 3: Performance comparison
There are two types of Processors. First, consider a Processor without cache and its main memory
access time is 20 cycles and 40% instructions require memory data access. For a Processor with
cache, we can assume that the cache access time is 2 cycles, hit rates of 0.85 for instructions and
0.90 for data. Assume miss penalty is 13 cycles
Compare times of 250 instructions. What can you conclude from the ratio?
(30 points) Problem 4.
Provide answers for Exercise 6.6.