Design for Testability Theory and Practice

Lecture 6: Combinational
ATPG

Copyright 2001, Agrawal & Bushnell

ATPG problem
Example
Algorithms
Multi-valued algebra
D-algorithm
Podem
Other algorithms
ATPG system
Summary
Day-1 PM Lecture 6

ATPG Problem

ATPG: Automatic test pattern generation

Given

A circuit (usually at gate-level)

A fault model (usually stuck-at type)

Find

A set of input vectors to detect all modeled faults.

Core solution: Find a test vector for a given fault.

Combine the core solution with a fault
simulator into an ATPG system.

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Day-1 PM Lecture 6

What is a Test?
Fault activation
Fault effect

Primary inputs
(PI)

X
1
0
0
1
0
1
X
X

Combinational circuit
1/0

Stuck-at-0 fault
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Day-1 PM Lecture 6

1/0

Primary outputs
(PO)

Path sensitization

Multiple-Valued Algebras
Symbol

D
D
0
1
X
G0
G1
F0
F1

Fault-free Faulty
Alternative
Representation circuit
Circuit
1/0
0/1
0/0
1/1
X/X
0/X
1/X
X/0
X/1

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1
0
0
1
X
0
1
X
X
Day-1 PM Lecture 6

0
1
0
1
X
X
X
0
1

Roths
Algebra
Muths
Additions

An ATPG Example
1 Fault activation
2 Path sensitization
3 Line justification

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Day-1 PM Lecture 6

ATPG Example (Cont.)

1 Fault activation
2 Path sensitization
3 Line justification
1

D
D

D
0

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Day-1 PM Lecture 6

D
1

ATPG Example (Cont.)

1 Fault activation
2 Path sensitization
3 Line justification
1

D
D

Conflict

1
1

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Day-1 PM Lecture 6

ATPG Example (Cont.)

Backtrack

1 Fault activation
2 Path sensitization
3 Line justification

0
1

D
D

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Day-1 PM Lecture 6

ATPG Example (Cont.)

1 Fault activation
2 Path sensitization
3 Line justification
0
0
1

D
D

1
Test found
Copyright 2001, Agrawal & Bushnell

Day-1 PM Lecture 6

D-Algorithm (Roth
1967)

Use D-algebra
Activate fault
Place a D or D at fault site
Justify all signals
Repeatedly propagate D-chain toward POs through a gate
Justify all signals
Backtrack if
A conflict occurs, or
All D-chains die
Stop when
D or D at a PO, i.e., test found, or
Search exhausted, no test possible

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Day-1 PM Lecture 6

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Example: Fault A sa0

Step 1 Fault activation Set A = 1

D
D
D-frontier = {e, h}

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11

Example Continued

Step 2 D-Drive Set f = 0

0
1

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12

Example Continued

Step 3 D-Drive Set k = 1

1
D
0
1

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13

Example Continued

Step 4 Consistency Set g = 1

1
1

0
D
1

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14

Example Continued

Step 5 Consistency f = 0 Already set

0
1

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Example Continued

Step 6 Consistency Set c = 0, Set e = 0

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0
D

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16

Example: Test Found

Step 7 Consistency Set B = 0

Test: A = 1, B = 0, C = 0, D = X

X
1
1

0
0
1

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0
D

Day-1 PM Lecture 6

17

Podem (Goel, 1981)

Podem: Path oriented decision making

Step 1: Define an objective (fault activation, D-drive, or line
justification)
Step 2: Backtrace from site of objective to PIs (use
testability measures guidance) to determine a value for a PI
Step 3: Simulate logic with new PI value
If objective not accomplished but is possible, then
continue backtrace to another PI (step 2)
If objective accomplished and test not found, then
define new objective (step 1)
If objective becomes impossible, try alternative
backtrace (step 2)
Use X-PATH-CHECK to test whether D-frontier still there
a path of Xs from a D-frontier to a PO must exist.

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Day-1 PM Lecture 6

18

Podem Example
3. Logic simulation for A=0

2. Backtrace A=0

1. Objective 0

S-a-1
(9, 2)

4. Objective possible but not accomplished

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19

Podem Example
(Cont.)
6. Logic simulation for A=0, B=0
5. Backtrace B=0

1. Objective 0

0
0
0

S-a-1
0

(9, 2)

7. Objective possible but not accomplished

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Day-1 PM Lecture 6

20

Podem Example
(Cont.)
9. Logic simulation for E=0
8. Backtrace E=0

1. Objective 0

0
0
0

0
0

S-a-1
0

(9, 2)

10. Objective possible but not accomplished

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Day-1 PM Lecture 6

21

Podem Example
(Cont.)
12. Logic simulation for D=0

1. Objective 0

0
0
0

0
0

S-a-1
0

0
13. Objective accomplished
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Day-1 PM Lecture 6

0
(9, 2)

11. Backtrace D=0

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An ATPG System
Random pattern
generator
Fault simulator
yes
Save
patterns

yes

Fault
coverage
improved?

no

Random
patterns
effective?

no

Deterministic
ATPG (D-alg.
or Podem)

Stop if fault coverage goal achieved

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Day-1 PM Lecture 6

23

Summary

Most combinational ATPG algorithms use D-algebra.

D-Algorithm is a complete algorithm:

Podem is also a complete algorithm:

Finds a test, or
Determines the fault to be redundant
Complexity is exponential in circuit size
Works on primary inputs search space is smaller than that of
D-algorithm
Exponential complexity, but several orders faster than Dalgorithm

More efficient algorithms available FAN, Socrates, etc.

See, M. L. Bushnell and V. D. Agrawal, Essentials of Electronic

Testing for Digital, Memory and Mixed-Signal VLSI Circuits,
Springer, 2000, Chapter 7.

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Day-1 PM Lecture 6

24

Exercise 2: Lectures
4-6

For the circuit shown above

Determine SCOAP testability measures.

Derive a test for the stuck-at-1 fault at the output of
the AND gate.
Using the parallel fault simulation algorithm,
determine which of the four primary input faults are
detectable by the test derived above.

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Day-1 PM Lecture 6

25

Exercise 2: Answers
SCOAP testability measures, (CC0, CC1) CO, are shown below:

(1,1) 4
(1,1) 4
(1,1) 3

(2,3) 2

(4,2) 0

(1,1) 3

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Day-1 PM Lecture 6

26

Exercise 2: Answers
Cont.
A test for the stuck-at-1 fault shown in the diagram is 00.

0
0

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s-a-1

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27

Exercise 2: Answers
Cont.
Parallel fault simulation of four PI faults is illustrated below.
Fault PI2 s-a-1 is detected by the 00 test input.

00100

00000
00001

00001

PI2=0
No fault
PI1 s-a-0
PI1 s-a-1
PI2 s-a-0
PI2 s-a-1

00001

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00001

Day-1 PM Lecture 6

PI2 s-a-1 detected

PI1=0

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