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Module Divider - 8bit (Input CLK, Ce, SCLR, Output RFD, Input (7:0) Dividend, Divisor, Output (7:0) Quotient

This document describes a module for dividing 8-bit numbers. It contains a divider_8bit module that takes in 8-bit dividend and divisor inputs and outputs the 8-bit quotient and fractional results. A testbench module divider_8_tb is created to test the divider_8bit module by applying different input patterns and checking the output results.

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32 views5 pages

Module Divider - 8bit (Input CLK, Ce, SCLR, Output RFD, Input (7:0) Dividend, Divisor, Output (7:0) Quotient

This document describes a module for dividing 8-bit numbers. It contains a divider_8bit module that takes in 8-bit dividend and divisor inputs and outputs the 8-bit quotient and fractional results. A testbench module divider_8_tb is created to test the divider_8bit module by applying different input patterns and checking the output results.

Uploaded by

blessysara16
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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module divider_8bit(

input clk,ce,sclr,
output rfd,
input [7:0] dividend,divisor,
output [7:0] quotient,

output [7:0] fractional


);
div_mod d1 (
.clk(clk),
.ce(ce),
.sclr(sclr),
.rfd(rfd),
.dividend(dividend), // Bus [7 : 0]
.divisor(divisor), // Bus [7 : 0]
.quotient(quotient), // Bus [7 : 0]
.fractional(fractional));

endmodule
module divider_8_tb;

// Inputs
reg clk;
reg ce;
reg sclr;
reg [7:0] dividend;
reg [7:0] divisor;

// Outputs
wire rfd;
wire [7:0] quotient;
wire [7:0] fractional;

// Instantiate the Unit Under Test (UUT)


divider_8bit uut (
.clk(clk),
.ce(ce),
.sclr(sclr),
.rfd(rfd),
.dividend(dividend),
.divisor(divisor),
.quotient(quotient),
.fractional(fractional)
);

initial begin
// Initialize Inputs
clk = 1;
ce = 1;
sclr = 1;
dividend = 8'b00001000;
divisor = 8'b00000010;

// Wait 100 ns for global reset to finish


#100;
// Initialize Inputs
clk = 1;
ce = 1;

sclr = 0;
dividend = 8'b00001000;
divisor = 8'b00000010;

// Wait 100 ns for global reset to finish


#200;
clk = 1;
ce = 1;
sclr = 0;
dividend = 8'b00001100;
divisor = 8'b00000010;

// Wait 100 ns for global reset to finish


#200;
clk = 1;
ce = 1;
sclr = 0;
dividend = 8'b00001110;
divisor = 8'b00000100;

// Wait 100 ns for global reset to finish


#200;

// Add stimulus here

end

always #10 clk=~clk;

endmodule

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