Assignment-5 by Kaneria Dhaval: Verilog Code For Single Cycle Processor
Assignment-5 by Kaneria Dhaval: Verilog Code For Single Cycle Processor
Assignment-5 by Kaneria Dhaval: Verilog Code For Single Cycle Processor
ASSIGNMENT-5
BY KANERIA DHAVAL
Verilog Code For Single Cycle Processor
DATAPATH WITH CONTROLLER
PC VERILOG CODE
module ProgramCounter
(
input [4:0]d_in,
input reset, clk,
output reg [4:0] d_out
);
always @(posedge clk)
if (reset)
d_out <= 5'b00000;
else
d_out <= d_in;
endmodule
AC VERILOG CODE
module Accumulator
(input [7:0] d_in,
input load, clk,
output reg [7:0] d_out
);
always @(posedge clk)
if (load)
d_out <= d_in;
initial
d_out=8'h00;
endmodule
3'b001:
begin
rd_mem = 1'b1;
wr_mem = 1'b0;
ld_ac = 1'b1;
ac_src = 1'b0;//SUBTRACT
end
3'b010:
begin
rd_mem = 1'b1;
wr_mem = 1'b0;
ld_ac = 1'b1;
ac_src = 1'b0;//AND
end
3'b011:
begin
rd_mem = 1'b1;
wr_mem = 1'b0;
ld_ac = 1'b1;
ac_src = 1'b0;//OR
end
3'b100:
begin
rd_mem = 1'b1;
wr_mem = 1'b0;
ld_ac = 1'b1;
ac_src = 1'b0;//NOT
end
3'b101:
begin
rd_mem = 1'b1;
wr_mem = 1'b0;
ld_ac = 1'b1;
ac_src = 1'b0;//XOR
end
3'b110:
begin
rd_mem = 1'b1;
wr_mem = 1'b0;
ld_ac = 1'b1;
ac_src = 1'b0;//XNOR
end
3'b111:
begin
rd_mem = 1'b0;
wr_mem = 1'b0;
ld_ac = 1'b0;
ac_src = 1'b0;
pc_src=1'b1;
jmp_uncond=1'b1;//JUMP
end
default:
begin
rd_mem = 1'b0;
wr_mem = 1'b0;
ac_src = 1'b0;
pc_src = 1'b0;
ld_ac = 1'b0;
end
endcase //end case
end //end always
endmodule
initial
begin
dm_array[0] = 8'h01;
dm_array[1] = 8'h02;
dm_array[2] = 8'h03;
dm_array[3] = 8'h04;
dm_array[4] = 8'h05;
end
endmodule
wire rd_mem;
wire wr_mem;
wire [4:0] im_abus;
wire [4:0] dm_abus;
wire [7:0] dm_in_dbus;
wire [7:0] ac_out,alu_out;
wire [2:0] opcode;
CPU uut (
.clk(clk),.reset(reset),.rd_mem(rd_mem),.wr_mem(wr_mem),
.im_abus(im_abus),.im_dbus(im_dbus),.dm_abus(dm_abus),
.dm_in_dbus(dm_in_dbus),.dm_out_dbus(dm_out_dbus),.ac_out(ac_out),.alu_out(alu
_out),.opcode(opcode));
InstructionMemory IM (.abus(im_abus),.dbus(im_dbus));
DataMemory DM
(.rd(rd_mem),.wr(wr_mem),.abus(dm_abus),.in_dbus(dm_in_dbus),.out_dbus(dm_out_dbus)
);
initial
begin
clk = 0;
reset = 1;//im_dbus =8'hxx;dm_out_dbus = 8'b00000000;
#20 reset = 1'b0;
#500 $finish;
end
always
#10 clk = ~clk;
Endmodule
RTL DIAGRAM
Insideview of RTL
RTL OF CPU
RTL OF DATAPATH
Technology map
00
01
02
03
04
Data
01
02
03
04
05
21
42
63
84
A4
C4
EA
00
E0
FF
05
06
Instruction memory :
Location
Instruction 00
FF
03
07
FA
07