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Low Power ROM

This document discusses low power techniques for ROM architectures. It describes that NAND ROMs have high power dissipation while NOR ROMs have low power dissipation but are slower. It then outlines several low power techniques for ROM architecture, including hierarchical word lines, selective precharging of bit lines, minimizing zero terms through encoding, difference encoding, and using smaller ROMs. Circuit level techniques discussed are NMOS precharging and voltage scaling.

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Lucas Weaver
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114 views12 pages

Low Power ROM

This document discusses low power techniques for ROM architectures. It describes that NAND ROMs have high power dissipation while NOR ROMs have low power dissipation but are slower. It then outlines several low power techniques for ROM architecture, including hierarchical word lines, selective precharging of bit lines, minimizing zero terms through encoding, difference encoding, and using smaller ROMs. Circuit level techniques discussed are NMOS precharging and voltage scaling.

Uploaded by

Lucas Weaver
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Low Power ROM

Prepared By -: Manan

NAND and NOR ROM

NAND

NOR

Power
Dissipation

High

Low

Speed

Low

High

Power Sources in ROM

Low Power Techniques: Architecture

Hierarchical Word Line


Selective Precharge
Minimization of Zero Terms
Difference Encoding
Smaller ROMs

Hierarchical Word Line

Selective Precharge
Large capacitance is being switched per
cycle because every bit line is being
precharged high during the first part of the
cycle and many bit lines are discharged
even when these locations are not
accessed.
Through selective precharge only bit lines
which will be accessed are precharged.

Minimization of Zero Terms


Inverted ROM
Inverted Row
1 0 1 1 1 1 0 1

0 1 0 1 1 1 1 0 1

0 1 0 0 0 0 1 0

1 1 0 1 1 1 1 0 1

Original
Data

Encoded Bit

Difference Encoding
Difference encoding can be used to reduce
the whole size of the ROM core. For digital
filters and other applications the ROM is
accessed sequentially.
If the values between adjacent data do not
change significantly between one address
and the next, the ROM core can store the
difference between the data instead of the
whole value.

Smaller ROMs
A
better
implementation
can
be achieved if the
large coefficients are
stored in a wide ROM
with fewer address.
The small coefficients
are stored in narrow
ROM
with
many
addresses.
Locations
that
are
accessed
frequently
are stored in a small,
fast ROM, while the

Low Power Techniques: Circuit Level


NMOS Precharge
Bit lines are precharged to Vdd - Vt

Voltage Scaling

Thank You.

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