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LAB2

The document contains VHDL code for several basic digital logic components: a latch, D flip-flop, 4-to-1 multiplexer, 4-bit decoder, 3-bit serial-in serial-out shift register, and 4-bit parallel-in parallel-out shift register. Each component is defined by its entity, ports, and behavioral architecture using processes and if/case statements.

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Adeel Hanif
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© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
15 views

LAB2

The document contains VHDL code for several basic digital logic components: a latch, D flip-flop, 4-to-1 multiplexer, 4-bit decoder, 3-bit serial-in serial-out shift register, and 4-bit parallel-in parallel-out shift register. Each component is defined by its entity, ports, and behavioral architecture using processes and if/case statements.

Uploaded by

Adeel Hanif
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
entity latch is
Port ( D : in STD_LOGIC;
clock : in STD_LOGIC;
y : out STD_LOGIC);
end latch;
architecture Behavioral of latch is
begin
process(D,clock)
begin
if clock = '1' then
y<=D;
end if;
end process;
end Behavioral;

D-flip Flop:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity DFF is
Port ( d : in STD_LOGIC;
clk : in STD_LOGIC;
y : out STD_LOGIC);
end DFF;
architecture Behavioral of DFF is
begin
process(d,clk)
begin
if (clk' event and clk = '1') then
y<=d;
end if;
end process;
end Behavioral;

MUX:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux4x1 is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : in STD_LOGIC;
d : in STD_LOGIC;
s : in STD_LOGIC_VECTOR (1
downto 0);
y : out STD_LOGIC);
end mux4x1;
architecture Behavioral of mux4x1 is
begin
process(a,b,c,d,s)
begin
if s="00" then
y<=a;
elsif s="01" then
y<=b;
elsif s="10" then
y<=c;
elsif s="11" then
y<=d;
end if;
end process;
end Behavioral;

Decoder:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Decoder is
Port ( x : in STD_LOGIC_VECTOR
(1 downto 0);
a : out STD_LOGIC;
b : out STD_LOGIC;
c : out STD_LOGIC;
d : out STD_LOGIC);
end Decoder;
architecture Behavioral of Decoder is
begin
Ad
:process (x)
begin
a<='0';b<='0';c<='0';d<='0';
case x is
when "00" =>
a<='1';
when "01" =>
b<='1';

when "10" =>


c<='1';
when "11" =>
d<='1';
when others =>
a<='0';b<='0';c<='0';d<='0';
end case;
end process;
SiSO:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

SISO:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity serialOut is
Port ( q : in STD_LOGIC;
clock : in STD_LOGIC;
yout : out STD_LOGIC);
end serialOut;
architecture Behavioral of serialOut
is
component DFF is
Port ( d : in STD_LOGIC;
clk : in STD_LOGIC;
y : out STD_LOGIC);
end component;
signal s : std_logic_vector(2 downto
0);
begin
Map0: DFF port map
(d=>q,
clk=>clock,
y=>s(0));
Map1: DFF port map
(d=>s(0),
clk=>clock,
y=>s(1));
Map2: DFF port map
(d=>s(1),
clk=>clock,
y=>s(2));
Map3: DFF port map
(d=>s(2),
clk=>clock,
y=>yout);
end Behavioral;

entity ParallelOut is
Port ( q : in STD_LOGIC;
yout : inout
STD_LOGIC_VECTOR (3 downto 0);
clock : in STD_LOGIC);
end ParallelOut;
architecture Behavioral of ParallelOut
is
component DFF is
Port ( d : in STD_LOGIC;
clk : in STD_LOGIC;
y : out STD_LOGIC);
end component;
begin
Map0: DFF port map
(d=>q,
clk=>clock,
y=>yout(3));
Map1: DFF port map
(d=>yout(3),
clk=>clock,
y=>yout(2));
Map2: DFF port map
(d=>yout(2),
clk=>clock,
y=>yout(1));
Map3: DFF port map
(d=>yout(1),
clk=>clock,
y=>yout(0));
end Behavioral;

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