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Assignment-3 Support Files

The document contains the description and code for a MIPS processor core including: - The main decoder control outputs and states for different instructions. - A table showing the instruction trace for a sample program. - Verilog code for the ALU, register file, control unit, program counter, and other modules.

Uploaded by

Rahul Jaiswal
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© © All Rights Reserved
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Download as DOC, PDF, TXT or read online on Scribd
94 views

Assignment-3 Support Files

The document contains the description and code for a MIPS processor core including: - The main decoder control outputs and states for different instructions. - A table showing the instruction trace for a sample program. - Verilog code for the ALU, register file, control unit, program counter, and other modules.

Uploaded by

Rahul Jaiswal
Copyright
© © All Rights Reserved
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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Main Decoder Control outputs

IRWrite

RegWrite

ALUSrcA

Branch

IorD

MemtoReg

ALUSrcB[1:0
]
RegDst

PCSrc[1:0]

ALUOp[1:0]

01

00

00

0x5010

1(Decode)

11

00

00

0x0030

2(MemAdr)

10

00

00

0x0420

3(MemRd)

00

00

00

0x0100

4(MemWB)

00

00

00

0x0880

5(MemWr)

00

00

00

0x2100

6(RtypeEx)

00

00

10

0x0402

7(RtypeWB)

00

00

00

0x0840

8(BeqEx)

00

01

01

0x0605

9(AddiEx)

10

00

00

0x0420

10(AddiWB)

00

00

00

0x0800

11(JEx)

00

10

00

0x4008

State

FSM Control
Word

MemWrite
0

PCWrite
1

(Name)

0(Fetch)

Table 1

Expected Instruction Trace

Cycle

Reset

PC

Instr

(FSM) state

SrcA

SrcB

ALUResult

Zero

00

00

04

04

04

addi
20080042

04

108

10C

04

addi
20080042

00

42

42

04

addi
20080042

10

04

00

04

04

addi
20080042

04

04

08

08

j
08000008

08

20

28

08

j
08000008

11

08

00

08

20

j
08000008

20

04

24

24

beq
1000fff9

24

FFFF
FFE4

08

10

24

beq
1000fff9

00

00

00

11

08

beq
1000fff9

08

04

0C

12

0C

addi
20090004

0C

10

1C

13

0C

addi
20090004

00

04

04

14

0C

addi
20090004

10

0C

00

0C

15

0C

0C

04

10

16

10

10

0001
4088

00014098

17

10

42

04

3E

18

10

10

04

14

19

10

10

04

14

20

14

14

0001
6094

000160A8

21

14

3E

42

7E

22

14

14

42

56

23

14

14

18

24

18

18

B0

C8

25

18

00

2C

2C

26

18

18

7E

96

27

18

18

04

1C

20090004
01095022
01095022
01095022
sub
01095022
01485825
01485825
01485825
01485825
sw
ac0b002c
ac0b002c
ac0b002c

ac0b002c

28

1C

29

1C

30

1C

31

1C

32

33

lw
8d2c0028

1C

A0

BC

04

28

2C

1C

00

1C

lw
8d2c0028

1C

00

1C

1C

lw
8d2c0028

1C

04

20

20

j
08000007

20

1C

3C

34

20

j
08000007

11

20

00

20

35

1C

j
08000007

1C

04

20

36

20

j
08000007

20

1C

3C

37

20

j
08000007

11

20

00

20

8dc2c0028
8dc2c0028

Table 2

Verilog Code
`timescale 100us/1ps
module alu_32_bit(input [31:0]a,input [31:0]b,input [2:0]sel,output
[31:0]y,output z,output ov);
wire [31:0]b1;
assign b1=(sel[2])?(~b):b;
assign d=(sel==3'd6)?1'b1:1'b0;
wire [31:0]ornot;
wire [31:0]andnot;
wire [31:0]c;
wire [31:0]slt_equater;
addersub AA1(a,b1,d,c);
ornot AA2(a,b1,ornot);
andnot AA3(a,b1,andnot);
slt_equater AA4(a,b1,slt_equater);
assign z=~(|y);

assign ov=y[31]^ y[30]^ y[29];


assign y=((~sel[0])&(~sel[1]))?andnot:((sel[0])&(~sel[1]))?ornot:
((~sel[0])&(sel[1]))?c:slt_equater;
endmodule
module addersub (input [31:0] a, input[31:0] b, input d,output
[31:0] c1);
wire[31:0] c2;
wire c3,c4;
assign {c3,c2}=a+b;
assign {c4,c1}=c2+d;
endmodule
module ornot (input [31:0] a, input [31:0] b, output [31:0] ornot);
assign ornot=a | b;
endmodule
module andnot (input [31:0] a, input [31:0] b, output [31:0]
andnot);
assign andnot= a & b;
endmodule
module slt_equater (input [31:0] a, input [31:0] b, output [31:0]
slt_equater);
wire cry;
wire [31:0] c1;
assign {cry,c1}=a+(b+1);
assign slt_equater = 00000000000000000000000000000000 + c1[31];
endmodule

module MIPS_MC(input clk, input reset,output reg [31:0]PC, output


[31:0] ALUResult);
reg [31:0] Instr;
wire IorD,PCWrite,PCWriteCond,MemtoReg,MemWrite,MemRead,IRWrite,
RegDst, RegWrite;
wire [1:0] ALUOp,PCSource;
wire [2:0] ALUControl;
wire [1:0]ALUSrcB;
wire [1:0]PCSrc;
wire [31:0] writefromdata1;
wire [31:0]readfromdata1;
wire [31:0]readfromdata2;
wire [4:0]Rd;
reg [31:0]A;
reg [31:0]B;

wire [31:0]PC_out;
wire [31:0]SrcA;
wire [31:0]SrcB;
wire [31:0]Sign_extend_data;
reg [31:0]ALUOut;
wire Zero;
wire [31:0]Address;
wire [31:0] WriteData;
wire [31:0] ReadData;
wire
wire
wire
wire
wire
wire
wire

[31:0]PCplus4;
[31:0]In_4=32'd4;
[31:0] Shift32bit_left_2_out_branch;
[27:0] Shift_left_2_out_jump;
[31:0] PCBranch;
[31:0]PC_out_Branch_or_PCplus4;
[31:0]PCJump;

wire
wire
wire
wire

out;
PCen;
[31:0]RD;
[14:0]FSM_COntrol_Word;

wire [31:0]instrctnmemaddr;
reg [31:0]memdatareg;
wire ALUSrcA;
always@(posedge clk)
begin
if(reset)
PC<=32'd0;
else
begin
if(PCen)
PC<=PC_out;
end
A<=readfromdata1;
B<=readfromdata2;
ALUOut<=ALUResult;
memdatareg<=RD;
if(IRWrite)
Instr<=RD;
end
assign
FSM_COntrol_Word={PCWrite,MemWrite,IRWrite,RegWrite,ALUSrcA,PCWriteC
ond,IorD,MemtoReg,RegDst,ALUSrcB,PCSource,ALUOp};

Shift32bit_left_2
S_L_2_Branch(Sign_extend_data,Shift32bit_left_2_out_branch);

Shift26bit_left_2 S_L_2_Jump(Instr[25:0],Shift_left_2_out_jump);
assign PCJump={PC[31:28],Shift_left_2_out_jump};
assign PC_out=((PCSource==2'b00)?ALUResult:((PCSource==2'b01)?
ALUOut:((PCSource==2'b10)?PCJump:PC_out)));
mainmem I_M(instrctnmemaddr[7:2] ,B , MemWrite,MemRead,RD);
CntrlUnit
Control_U(clk,reset,Instr[31:26],IorD,PCWrite,PCWriteCond,MemtoReg,M
emWrite,MemRead,IRWrite, PCSource, ALUOp, ALUSrcB, ALUSrcA, RegDst,
RegWrite);
and(PC_update,PCWriteCond,Zero);
or(PCen,PC_update,PCWrite);
assign instrctnmemaddr=(IorD)?ALUOut:PC;
assign Rd=(RegDst)?Instr[15:11]:Instr[20:16]; //for Rt->Rd
Register_File R_F(clk,reset, Instr[25:21], Instr[20:16], Rd ,
writefromdata1,RegWrite,readfromdata1, readfromdata2);
assign SrcA=(ALUSrcA)?A:PC;
assign Sign_extend_data =
{Instr[15],Instr[15],Instr[15],Instr[15],Instr[15],Instr[15],Instr[1
5],Instr[15],Instr[15],Instr[15],Instr[15],Instr[15],Instr[15],Instr
[15],Instr[15],Instr[15],Instr[15:0]};
assign SrcB=((ALUSrcB==2'b00)?B:((ALUSrcB==2'b01)?32'd4:
((ALUSrcB==2'b10)?Sign_extend_data:Shift32bit_left_2_out_branch)));
ALUCntrlUnit A_U(ALUOp,Instr[5:0],ALUControl);
alu_32_bit alu(SrcA, SrcB, ALUControl, ALUResult, Zero, Ov);

assign writefromdata1=(MemtoReg)?memdatareg:ALUOut;
endmodule
module Shift32bit_left_2(input [31:0] Sign_extend_data,output [31:0]
Shift32bit_left_2_out_branch);
assign Shift32bit_left_2_out_branch={Sign_extend_data[29:0],2'b00};
endmodule
module Shift26bit_left_2(input [25:0] Jump_data_in ,output [27:0]
Shift_left_2_out_jump);

assign Shift_left_2_out_jump={Jump_data_in[25:0],2'b00};
endmodule
module Add(input [31:0] a, input[31:0] b,output [31:0] c);
assign c=a+b;
endmodule

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