Digital Systems - 6: Pere Pal' A - Alexis L Opez
Digital Systems - 6: Pere Pal' A - Alexis L Opez
March 2015
Datapath
Control Section
A
B
C
D
M1
M0
clk
rst
6
00
01
mx
10
11
00
D
R
Datapath
signal
signal
signal
signal
A ,B ,C ,D , mx
: s t d _ l og i c _ v e c t o r (3 downto 0);
clk , rst
: std_logic ;
M
: s t d _ l o g i c _ v e c t o r (1 downto 0);
addA , addB , addOut ,
Din ,Q , S
: s t d _ l o g i c _ v e c t o r (5 downto 0);
begin
with M select
mx <= A when " 00 " , B when " 01 " ,
C when " 10 " , D when " 11 " , " ---- " when others ;
addA
<= Q ;
addB
<= " 00 " & mx ;
addOut <= s t d _ l o gi c _ v e c t o r ( unsigned ( addA )+ unsigned ( addB ));
Din
<= addOut ;
process ( clk )
begin
if rising_edge ( clk ) then
if rst = 1 then
Q <= " 000000 " ;
else
Q <= Din ;
end if ;
end if ;
end process ;
S <= Q ;
end ;
Control Section
Control Signals
I
Indicate completion
do_add
0
1
0
1
State Transitions
Present State
A
B
C
D
E
Next State
A, if do_add=1
B, if do_add=0
A, if do_add=1
C, if do_add=0
A, if do_add=1
D, if do_add=0
A, if do_add=1
E, if do_add=0
A, if do_add=1
E, if do_add=0
Actions
M <= "00"
add_done <= 0
M <= "01"
add_done <= 0
M <= "10"
add_done <= 0
M <= "11"
add_done <= 0
M <= "--"
add_done <= 1
Simulation Results
I add_done
Additional signal
dstate