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Digital Systems - 6: Pere Pal' A - Alexis L Opez

The document describes a sequential datapath and control section to add 4 numbers of 4 bits using only one adder. It includes: 1) A datapath with 4 input signals (A, B, C, D), a multiplexer to select the next input, an adder, register to store the result. 2) A control section with 5 states (A, B, C, D, E) to sequentially select the next input and trigger the addition. It uses a state machine and control signals to synchronize the datapath. 3) Verilog code for the datapath and state machine logic. 4) Simulation results showing the addition of 1+2+4+8 and control signals.

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67 views7 pages

Digital Systems - 6: Pere Pal' A - Alexis L Opez

The document describes a sequential datapath and control section to add 4 numbers of 4 bits using only one adder. It includes: 1) A datapath with 4 input signals (A, B, C, D), a multiplexer to select the next input, an adder, register to store the result. 2) A control section with 5 states (A, B, C, D, E) to sequentially select the next input and trigger the addition. It uses a state machine and control signals to synchronize the datapath. 3) Verilog code for the datapath and state machine logic. 4) Simulation results showing the addition of 1+2+4+8 and control signals.

Uploaded by

ingjojeda
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Digital Systems - 6

Pere Pal`a - Alexis L


opez
iTIC http://itic.cat

March 2015

Sequential Datapath and Control Section


I

Objective: To add 4 numbers of 4 bits

Restriction: Only one adder.

Datapath

Control Section
A
B
C
D
M1
M0
clk
rst

6
00
01

mx

10
11

00

D
R

Datapath
signal
signal
signal
signal

A ,B ,C ,D , mx
: s t d _ l og i c _ v e c t o r (3 downto 0);
clk , rst
: std_logic ;
M
: s t d _ l o g i c _ v e c t o r (1 downto 0);
addA , addB , addOut ,
Din ,Q , S
: s t d _ l o g i c _ v e c t o r (5 downto 0);

begin
with M select
mx <= A when " 00 " , B when " 01 " ,
C when " 10 " , D when " 11 " , " ---- " when others ;
addA
<= Q ;
addB
<= " 00 " & mx ;
addOut <= s t d _ l o gi c _ v e c t o r ( unsigned ( addA )+ unsigned ( addB ));
Din
<= addOut ;
process ( clk )
begin
if rising_edge ( clk ) then
if rst = 1 then
Q <= " 000000 " ;
else
Q <= Din ;
end if ;
end if ;
end process ;
S <= Q ;
end ;

Control Section
Control Signals
I

Trigger the process

Indicate completion

State Transition Diagram


0

Depending on the signal

do_add

0
1

0
1

State Transitions

Present State
A
B
C
D
E

Next State
A, if do_add=1
B, if do_add=0
A, if do_add=1
C, if do_add=0
A, if do_add=1
D, if do_add=0
A, if do_add=1
E, if do_add=0
A, if do_add=1
E, if do_add=0

Actions
M <= "00"
add_done <= 0
M <= "01"
add_done <= 0
M <= "10"
add_done <= 0
M <= "11"
add_done <= 0
M <= "--"
add_done <= 1

State Machine Coding


type t_state is ( sA , sB , sC , sD , sE );
signal pr_state , nx_state : t_state ;
process ( clk )
begin
if rising_edge ( clk ) then
pr_state <= nx_state ;
end if ;
end process ;
rst <= do_add ;
process ( pr_state , do_add )
begin
case pr_state is
when sA = > -- actions c o r r e s p o n d i n g to state A
M
<= " 00 " ;
-- 1: Outputs . Caution !!!
add_done <= 0 ;
-- Do not forget any output !
if do_add = 1 then
nx_state <= sA ;
-- 2: Compute next state
else
-- d e p e n d i n g on present state
nx_state <= sB ;
-- and the input ( s )
end if ;
when sB = > -- actions c o r r e s p o n d i n g to state B
...

Simulation Results

Showing 1+2+4+8 = x0F = 001111

I add_done

signals when the result is available.

Has to be read on the next clock edge!

Additional signal

dstate

created to debug the state.

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