Scribd
Upload
51 views6 pages

Digital Systems - 3: Pere Pal' A - Alexis L Opez

This document discusses different types of D flip-flops in VHDL. It begins with a basic D flip-flop that uses a process statement with a clock signal to latch the D input onto the Q output on each rising edge of the clock. It then discusses using process sensitivity lists, adding a clock enable, and implementing asynchronous and synchronous resets to modify the basic D flip-flop behavior.

Uploaded by

ingjojeda
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
51 views6 pages

Digital Systems - 3: Pere Pal' A - Alexis L Opez

This document discusses different types of D flip-flops in VHDL. It begins with a basic D flip-flop that uses a process statement with a clock signal to latch the D input onto the Q output on each rising edge of the clock. It then discusses using process sensitivity lists, adding a clock enable, and implementing asynchronous and synchronous resets to modify the basic D flip-flop behavior.

Uploaded by

ingjojeda
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 6

Digital Systems - 3

Pere Pal`a - Alexis L


opez
iTIC http://itic.cat

February 2015

D Flip-Flop

CLK
D

D
Q

signal d , q
: std_logic ;
...
my_dff : process ( clk ) is
begin
if rising_edge ( clk ) then
q <= d ;
end if ;
end process my_dff ;

Process statement
name1 : process (a ,b , c ) is
begin
sequential statement 1 a ;
sequential statement 2 a ;
...
end process name1 ;
name2 : process (c ,d , e ) is
begin
sequential statement 1 b ;
sequential statement 2 b ;
...
end process name1 ;
I

Process name1 is (only!) triggered when a, b or c changes. This


is the sensitivity list.

Inside a process, the statements are executed in order.

Process

name1

is executed concurrently with process

name2

D Flip-Flop on a bus with clock enable


CLK
D
E

D
E
Q

signal d , q
: s t d _ l o g i c _ v e c t o r (7 downto 0);
signal ce
: std_logic ;
...
my_dff : process ( clk ) is
begin
if rising_edge ( clk ) then
if ce = 1 then
q <= d ;
end if ;
end if ;
end process my_dff ;

D Flip-Flop with Asynchronous Reset


CLK
D
R

D
R
Q

signal d , q
: s t d _ l o g i c _ v e c t o r (7 downto 0);
signal reset : std_logic ;
...
my_dff : process ( clk , reset ) is
begin
if reset = 1 then -- reset o v e r r i d e s e v e r y t h i n g !
q <= " 00000000 " ;
elsif rising_edge ( clk ) then
q <= d ;
end if ;
end process my_dff ;

D Flip-Flop with Synchronous Reset


CLK
D
R

D
R
Q

signal d , q
: s t d _ l o g i c _ v e c t o r (7 downto 0);
signal reset : std_logic ;
...
my_dff : process ( clk ) is
begin
if rising_edge ( clk ) then
if reset = 1 then
q <= ( others = > 0 );
else
q <= d ;
end if ;
end if ;
end process my_dff ;

You might also like