Power Integrity analysis techniques to

get the best system performance at

the cheapest cost.
Tanit Virutchapunt
[email protected]

Power Integrity Specialist

Sigrity, Inc.
EDAPS2009 Shenzhen, China
Dec 2nd, 2009

What is the best power plane performance?

What is best DC power plane performance?

Devices see voltage closet to nominal voltage
 Low IR drop
Well balanced DC voltages among devices on the same rail

Low Temperature Rise on Metal
 Low Current Density

Power Efficiency
 Low Power Loss
What is best AC power plane performance?

Low noise
 Low loop inductance
 Low and Flat impedance

Best Performance VS Cost

Best power plane performance comes with a price. How to get the best power
plane without adding extra cost to the design is challenging to designer.

ST
E
B

$
3

What to look for in DC analysis?

4

IR drop target
How to budget IR drop and AC noise margin?
Poor design

Good design

IR drop

Total
margin

IR drop
AC noise
margin

Total
margin

AC noise margin

IR drop margin should be less than AC noise margin since the AC

noise usually a lot harder to be controlled in the margin.
5

Excessive IR drop due to narrow and long traces

Functional problem can be
caused by too much IRdrop
even in the low power .

IR drop target is 66mV

Voltage
+3.3VCS

refdes
U3_CP1
U2_CP0
J23_GX1
J24_GX2
J54_DASD
J49_RAID
U18_FSP1
J25_ENET0
U31_HMC0
U30_HMC0

criteria
Breif description
P6
P6
GX CARD
GX CARD
DASD backplane
RAID card
FSP1 chip
ENET card
HMC chip
HMC chip

Max current (A)

0.250
0.250
0.218
0.218
0.006
0.006
0.51
0.006
0.012
0.012

SIGRITY Confidential

66mV (2%)
IR drop (mV)
-160
-115
-113
-111
-29
-13
-2.0
-1.4
-1.2
-1.0

159% over the target

Excessive IR drop due to DC resistance on passive

components

There is no such thing as zero ohm resistor.

Excessive IR drop on vias

5mV drop on each via
VRM

10mV drop
IC

2.4A flows into each via

8

Understand Temperature Rise on copper

caused by current flow on the copper

Thickness = 0.5oz

Current Density VS Width

Current VS Area
IPC-2152 spec gives relationship
between Temperature Rise VS
Cross-session of copper.

Trace has an uniform cross-session thus

IPC spec is straight forward.
Shape has different cross-sessions at
different locations, IPC spec is no longer
straight forward.

Same Current

100 sq.mil
30c

5A

500
sq.mil
5c

5A

With the same current flow on the plane, narrower plane will cause more heat.
10

Same
Temperature

100
sq.mil
30c

500 sq.mil
30c

5A
12A
To keep the same temperature rise on copper, wider plane can have more current.
11

Same Current
Density
100 mil
9c

500 mil
32c

heat
heat

30mA/mil^
2

30mA/mil^
2

With the same current density flowing on the plane at different width,
the wider plane will cause more heat on the copper since there is less
area heat can dissipate.
12

Same Temperature

100 mil
30c

56mA/mil^2

500 mil
30c

28mA/mil^2

To keep the same temperature rise on copper, narrower plane can have higher
current density.
13

Smoke or Fire is number#1 concern,

what would happen if this design were built?

Temperature Rise = 300c

14

Localize Heat in low power net

This low power rail can cause excessive
current density on the copper plane because
of the narrow shape.

15

Power Loss
Power Loss is important in all designs
especially products that use battery.

High power loss area

16

Devices should see voltage closet to a nominal voltage

2A

0.5A

0.5A

0.5A

0.5A

1A
1A
1A
1A

4A
10A

5A

4A
2A

0.5A

0.5A

0.5A

0.5A

VRM
With DC resistance on the plane that causes IR drop from power source to
devices, actual voltages at the devices will be less than the nominal voltage.
17

Power Source location and voltage output setting

are important
1.3V

1)

1.5V

200mV drop
1A

Power Source

1.5V

2)

1.7V

200mV drop
1A

1.65V

1.5V

3)

150mV drop
1A

1.5V

L/4

1.5V

1.575V
75mV drop

75mV drop

1A

1A
L/2

5)

L/2

R2

R1

VRM is at a location where R2*I2 = R1*I1

I1

I2
L2

6)

1.75V

100mV
1A

3L/4

4)

Device
Current Flow

L1

1.5V

1.5V

1A

1A

1.552V

1.5V
1A

52mV on each direction

From regulator

7)

1.5V

1.5V

1A

1A

1.56V

1.5V
2A

60mV on each direction

From regulator

18

Impossible to place power source in the best

location for all devices
Mechanical requirement forces
connectors to this place

19

How to improve the power plane

performance without adding extra cost?

20

How to identify copper areas that need to be

improved when DC voltage is failing?
Improving high current density area can help three things:
1. Reduce Resistance in this area
2. Reduce current density which will make copper cooler
3. Cooler copper will make copper resistivity lower which will make even
less resistance in this area
Plane Voltage Distribution Plot

Sink 5

Sink 0

VRM

Sink 4

5.25 V

Plane Current Density Plot

Sink 3
Sink 2

2nd
3rd

Sink 1

1st

4.75V
Underflow color, Voltage below 4.75V

Current density plot is used to identify areas

that should be used to add copper to
improve IRdrop.
21

How to improve Power Efficiency?

Identify high power loss areas in the design.
Power Loss plot can be used to pinpoint high power loss area.
High Power Loss area
3A

Regulator

5A

1A each
Trace
Via
Plane

Top
15.75
8.48
73.94

L1
0
0.3
45.78

Total power loss

L2
0
0
666.06

Bottom
0
0
47.67

Total
15.75
8.78
833.45

%
2
1
97

857.98 mW
22

How to find the via that will trigger field failure?

23

Highest current vias from Thousand of vias

Identify vias that have high current flow.
Via Current plot can be used to pinpoint vias with high current flow.

5A

24

Optimize VRM sense line

to get the best DC voltage balance

25

Remote Sense Line is needed when the power

source cant be placed in the desired location
Voltage Sense
location

VR
M
10A

Without feedback voltage sense to VRM

Load sees 100mV below

nominal voltage (1V)

VR
M
10A

With feedback voltage sense to VRM

Load now sees

nominal voltage (1V)
26

Where to place the Sense Line when there are

more than one device on the power rail?
Voltage Sense
location

Voltage Sense
location
VR
M

1A

VR
M

10A

This device sees too high

voltage

1.08V

1A

10A

This device sees too low

voltage

1V

1V
0.93V

This device sees perfect

voltage

This device sees perfect

voltage
27

A typical way to find the optimal sense location

Chip1
(10A)

Chip2

Chip2
(1A)

Chip1

28

A better way to find the optimal sense

locations

[Patent Pending - U.S. Patent Application No. 12/468,807]

29

[Patent Pending - U.S. Patent Application No. 12/468,807]

Device1
Voltage Level

Optimal VRM
Output Voltage

Vout_VRM

Vnominal

Vdevice2
VRM

Device2

Objective = minimizing voltage differences between actual voltage at devices and nominal voltage
With this example, Objective = min{ (Vdevice1 - Vnominal1)2+(Vdevice2 - Vnominal2)2+(VdeviceN - VnominalN)2}

Vdevice1

1)

Start without any sense line

2)

Determine the optimal output voltage level of VRM that meets the objective

3)

With using the VRM output voltage level from (2) search meshes that have the nominal voltage.

4)

The meshes that have the nominal voltage is the optimal sense locations.

5)

Optimal Sense Location Tolerance maybe used to display sub-optimal sense locations.

Note that the rectangular meshes are used in the picture above to simplify the drawing and explanation.

30

Optimal Sense Locations (Green)

1A

10A

1.035V

Voltage Sense
location

0.965V

35mV

35m V

31

Example
Where are the Optimal Sense Locations ?

VRM connector

11 devices, 1A each
32

No sense line

Sense here

Sense here

Sense at U1

Optimal Sense Location

33

What to look for in AC analysis?

34

Flat and Low Power Plane Impedance

~200MHz

< 100MHz

< 500KHz

~1KHz

Note: frequency numbers here are

very rough estimated. They are
depending on each design.

Target Impedance

On-chip capacitance
Pkg decaps

Board Decaps

Bulk Capacitors

Frequency (Log scale)

Regulator

Power plane Impedance

Where the breaking frequencies of capacitors on a system?

35

Low Loop Inductance from capacitors to a

device

Loop Inductance = 1.2nH

Loop Inductance = 0.043nH

36

0402PKG Decap Mounting Inductance of

different fanout type

0.512nH

0.551nH

0.592nH

0.249nH

0.299nH
Via right next to
pad (may not
allow by Mfg)

1.012mm

0.4mm

0.35mm

Er = 4

0.5mm
37

Review Decap Mounting

TOP

BOTTOM

Total of 394 decap locations to be reviewed

38

Review Decap Mounting in a flash

TOP

BOTTOM

Total of 394 decap locations in review

39

Typical Decap Analysis

VS
Auto decap optimization
start
start
Setup Design
30 min
Setup Design
30 min
Perform Analysis
2 hr
Perform Analysis
2 hr
View Results
15 min
Perform Optimization
4-6 hr
done ???

stop
View Results
30 min

Modify Design
30 min
stop

Auto decap optimization

Typical Decap Analysis

40

Auto Decap Optimization explores the entire decap design space while
considering all critical design factors in much less engineering time.
Next decap
combination?
Combination#1

Combination#...

Combination#2

Combination#....

Combination#....

Combination#3

Combination#....

Combination#...

Combination#...

Combination#....

Combination#....

Combination#...

Combination#....

Combination#...

Combination#....

Combination#....

Combination#...

u2

Combination#....

Combination#....

Combination#...

u1

Combination#....

u3

Combination#....

Combination#....

u4

u17

u1

u2

u3

Combination#250,000

u4

u17

u1

u2

u3

u4

u17

Performance
(Self Z, Transfer Z)
Cost, Space
BOM control
Target Impedance
Device Weighting
Location Preference
41

Optimization Result
There are many decap schemes for users selection
Each scheme has a tradeoff between cost and performance

42

The decap solution from auto decap

optimization
Total Setup Time: = 8mins
Simulation Time: 1 min
Optimization Time: 0.5min
Total Time Spent = 10mins

Total Decap Cost = 5x0.004 + 2x0.005 + 4x0.0045 = $0.048

50mohm

Remove

10nF

45MHz

100nF

Conclusion

22nF

Cost = $0.048

# of decaps=11

BOM=3

Time = 10 mins
Performance = upto 45MHz

43

Compare results from two approaches

Typical Analysis

Plane Performance

Up to 40MHz

Decap
Optimization
Up to 45MHz

Cost

$0.053

$0.048

# of decaps

13

11

BOM

Total Time

42mins

10mins
44

A new decap solution to fix anti-resonance

power plane issue.

45

Power plane impedance seen by each device

U2

VRM

U1
U150

TOP

U1

BOT

U2

U150

46

A new decap solution yields better power plane

impedance and 14% cheaper.
U2

U2

U1

U1
U1

U150

U150

TOP
TOP

U2

U150
BOT

Before

BOT

After
47

Decap summary reports

*

Original Decap Summary Report

ID
10
17
18
20
21
Total

Part No.
C_10nF_0402_GRM155R71C104KA88
C_100nF_0603_GRM188R71C104KA01
C_10uF_1206_GRM31MR60J106KE19
C_1uF_0805_LLA219R70J105MA01L
C_1nF_0402_GRM155R71H102KA01

Capacitance (nF)
9.5
90.1
7099
1027
0.95
---

Size
0402
0603
1206
0805
0402
---

Quantity
43
10
10
2
3
68

Total Cost

1.32109

* NEW Decap Summary Report

ID Part No.
2 C_100nF_0402_GRM155R71C104KA88
4 C_220nF_0402_GRM155R60J224KE01
5 C_2p2uF_0402_GRM155R60J225ME15
6 C_470nF_0402_GRM155R60J474KE18
7 C_4p7uF_0603_GRM188R60J475KE19
8 C_1uF_0402_GRM155R60J105KE19
11 C_10uF_0603_GRM188R60J106ME47
17 C_100nF_0603_GRM188R71C104KA01
18 C_10uF_1206_GRM31MR60J106KE19
Total

Capacitance (nF)
100
195
1204
340
2740
620
4991
90.1
7099
---

Size
0402
0402
0402
0402
0603
0402
0603
0603
1206
---

Quantity
4
6
2
15
1
5
1
1
7
42

Total Cost

1.16586

48

Decap BOM simplification

(Reducing decap part numbers)

Limited numbers of reels to

be loaded into the machine.

Pick and Place machine

49

Decap BOM simplification

(Reducing decap part numbers)

U17
10 nF
47 nF
100 nF
220 nF
470 nF

U1

U2

U3

U4

50

Decap BOM simplification

(Reducing decap part numbers)
10 nF
47 nF
100 nF
220 nF
470 nF

Original Design
U17

U3

U1

U2

U4
Original Decaps
Optimized Decaps

51

Power Plane Noise improvement on Memory

DIMM with measurement verification

52

Observation and decap locations

Observe impedance at DRAM locations

This design is a high volume production. Cost should also be taken
into account during optimization.
SIGRITY Confidential

53

53

The resonant peak is reduce by 50% while

saving 6cents per board

U11
Original Design

50%

Scheme45(6cents saving)

SIGRITY Confidential

54

54

New Decap placement

Original Decaps

Scheme45

DecapLib_13 = 220pF 0402

DecapLib_14 = 2.2uF 0603
DecapLib_6 = 100nF 0402
DecapLib_@OPEN@ = no-pop

remove
SIGRITY Confidential

55

Time domain noise with real current

excitation from Scheme45
Original Design

78mV

18% noise
improved

9% cost
saving

Scheme45 (6cents saving)

64mV

SIGRITY Confidential

56

56

Noise amplitude

Noise from new decaps(Green) is less than noise from

original decaps(Red) across the frequency band.

Frequency
57

SI / PI expertise + automation = optimized design

BETTER and FASTER!
58