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ReducingCongestionWithICCompiler

ReducingCongestionWithICCompiler
DocId:020963Product:ICCompilerLastModified:08/05/2008

ReducingCongestionWithICCompiler
Congestionisaproblemthatyoufacewhendesigningchips.Congestionmeans
thatmoreroutingresourcesareneededthanyouactuallyhave.Congestioncan
occurlocallyinaportionofablockorgloballyforthewholeblock.Sometimes
yourdesignsarecongestedatdifferentlocationswithdifferentseverity.
Thisdocumentdescribeshowtosolvecongestionissues.
DivideandConquerApproach
Thedivideandconquerapproachresolvescongestionstepbystepanddoesnot
attempttosolveallcongestionproblemsatonce.Thisapproachcanappearto
bemoretimeconsuming,butitcanactuallytakelesstime.Youmightneedto
solveafewproblemsatthesametime,forexample,ahighutilizationissue,
adatapathstructureissue,oraportlocationissue.Someproblemsare
interdependentorinfluential,sosolvingthoseproblemsmightimprove
someresultsbutproduceotherpoorresults.Youshouldsaveyourresults
aftereachsuccessfulexperimentalstage.
Youshouldneitheroptimize(usingplace_optorpsynopt)norexplorecongestion
issuesofadesignatthesametime.Withlargedesigns,itmightbeuseful
tosegmentouttheproblematichierarchy(byusinggroupingcommandsinDesign
Compiler/DesignCompilertopographicalmode)andgeneratetheexpectedfloorplan
(byusingminimumphysicalconstraintoptions);thenworkstandaloneuntilyou
getthebestresults.
AvoidVeryHighUtilization
ThefirststepofdesignoptimizationinICCompilerisdonewithathinnetlist.
Thismeansthatthenetlistdoesnotcontainelementstobeaddedlaterin
theflowsuchasclocktreebuffers,holdfixingcells(buffers),andsoon.Area
shouldbepreservedtoaddtheseelementslater.Theamountoftheareatobesaved
dependsoneachdesign,butitisaround10percent.Timingissuesandwire
distancescandeterminetheamountoftheareaneeded.Indifficultsignalintegrity
cases,20percentshouldbesufficient.Therefore,itisrecommendedthatyouavoid
veryhighutilization.Ifyouhaveadesignwithveryhighutilization,takethe
followingactionstoeliminatepotentialproblemsresultedbyroutingcongestion
and/orinsufficientplacementarea:
1.Checkthedesignconstraints(bothtiminganddesignrulechecking).An
optimizeddesignthatcontainsmanylargecellsandbufferscouldindicatebad
constraints.Commandsthatmighthelpare:
check_timing
report_timing_requirementsignored
2.PerformnetlistreductionbyusingeitherDesignCompilerorICCompiler.
DesignCompiler:compilearea_efforthigh[inc]
ICCompiler:psynoptarea_recoveryarea_efforthigh[only_area_recovery]
ICCompiler:place_optarea_recovery
Settingphysopt_ultra_high_area_efforttotrueadverselyimpactsthedesign
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areawhenusedwithplace_optarea_recoveryeffortmediumorplace_opt
area_recoveryefforthigh.
Reducingthenumberofcellsinthedesignorevenspecifyingafewsubblocks
toreducethenumberofcells,youusefewerroutingresources.Toavoid
repeatingthisstepforeachstageintheflow(itmightcauselongerruntime),the
resultingreducednetlistshouldbesavedwithanewname.Thesavednetlist
becomesyourstartingpoint.
CongestionHotSpotsandBlockTiming
Someblockinspectionsrevealtimingissuesthatforcecellplacement.Asubblock
canhaveverytighttiminganddesignrulechecking(DRC)constraints,especiallya
pathwithmanylogiclevelsbetweenflipflopsorlatches.Inmanycases,the
tighttimingiscausedbytimingandDRCconstraintpropagationfromthetoplevel.
Thetoplevelconstraintsshouldbecheckedcarefully.Ifyoufindunjustified
constraints,applyadifferentDRCortimingconstrainttotheblock.
Youcanalsotryothertechniquessuchasusingcaseanalysis,settingfalse
pathormulticyclepathconstraints,addinginputdelaytotheassociatedclock,
orconstrainingtheports.
AutomaticCongestionHandling
IfyouwantICCompilertoresolvecongestionautomatically,followthebelow
steps.
SettheCongestionOptions
Forbestresults,youshouldproviderealisticnumbersfortherouting
availabilityofthemetallayers.Forexample,metal1ismostlyusedforcell
buildingandpowerandoftenhaslimitedavailabilityforrouting.
Tospecifytheroutingavailabilityforalayer,usethefollowingcommand:
set_congestion_optionslayer<layer>availability<percentage>\
coordinate[get_placement_area]
Thesesettingsaffectcongestionoptimizationandreporting.
ChecktheResults
Somelocationsinthedesignareexpectedtobecongestediftheyarenotwell
plannedforchannelandportareas.Thetreatmentfortheseareasisdescribed
inthe"FloorplanDrivenProblems"sectionthatfollows.
ViewtheASCIIcongestionreportgeneratedbythereport_congestioncommand.
YoucanalsoviewcongestioninformationintheGUI.
UsethecongestionOption
ICCompilerprovidespowerfulalgorithmstoresolvecongestion.Unlikethe
defaultbehaviorthattheplacerminimizeswirelength(thedefault)oroptimizes
pathlocationtomeettiming,thegoalofthealgorithmsistoreducecongestion.
Thealgorithmsareinvokedbyusingthecongestion*optionwiththepsynopt,
place_opt,create_placement,orrefine_placementcommandduringplacementstage.
Twoprimaryconcernswhenusingthecongestionremovalalgorithmsare:
1.Runtimeisincreased,socongestionremovalalgorithmsshouldbeinvoked
onlywhenneeded.
2.Congestionremovalalgorithmscanresultinlessoptimizeddesignfortiming.
Whenusingthecreate_placementandrefine_placementcommands,youcancontrol
thecongestioneffort.Thecongestion_effortoptiondetermineshowmucheffort
ICCompilerusestoresolvecongestion.Amediumeffortisthedefaultfor
tradeoffbetweenqualityandruntime.Formoredifficultdesigns,settingthe
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congestionefforttohighcausesalongerruntime.
Therecommendedwayofusingcongestionoptionsisasfollows:
MediumThemaximumroutingcongestionmightbegreaterthan100percent,
butmostroutingcongestionisbelow100percent.Congestionhotspotsarenot
largecomparedwiththeoverallfloorplansizeanddonotformlarge
masses.
HighThemaximumcongestionismuchhigherthan100percentandthe
routingcongestionisabove100percent.Hotspotsarelarge.
timing_drivencongestionTotradeoffbetweencongestionandtiming,
invokethetiming_drivenandcongestionoptions.Thetooltriesto
resolvetimingandcongestionproblemsconcurrently.Thefactthattimingand
congestioncostfunctionsarefullyrecognizedatallpointscangreatlybenefit
designswithbothtimingandcongestionproblems.
UseGlobalRouteBasedCongestion
Indifficultcases,youmightwanttouseamoreaccuratecongestioncalculation
basedonglobalroute.Thedefaultreport_congestioncommandisbasedonatradeoff
betweenaccuracyandfastruntime.Eventheresultofusingglobalroutecommand
mightnotdiffermuch,butitismoreaccurate.Usethefollowingcommand:
route_globalcongestion_map_only
UsetheHighEffortCongestionAlgorithm
ICCompilerprovidesanewhigheffortcongestionalgorithm.Toenablethis
algorithm,settheplacer_enable_high_effort_congestionvariabletotruebefore
yourunplace_optcongestionorpsynoptcongestion.Whenyouenablethe
higheffortcongestionalgorithm,ICCompilerdoesaverydetailed
congestiondrivenplacementandgeneratesalogasfollows:
100%done.
69%...75%...81%...88%...94%...69%...75%...81%...88%...94%...100%done.
[begininitializingdataforlegalitychecker]
Performingthepsynoptcongestionoptimizationwithoutthehigheffortcongestion
algorithmgivesyouthefollowinglog:
100%done.
69%...75%...81%...88%...94%...100%done.
FloorplanDrivenProblems
Thissectiondiscussesfloorplandrivenproblemssuchaschannels,macros,
powergrids,andportlocationchanges.
Channels(Slivers,Tunnels)CausingCongestionProblems
Achannelisdefinedastherouting(placement)areabetweenmacrosorthe
distancebetweenmacrosandthebordersofadesign.Youblockthechannelfrom
placementwithacompleteplacementblockage.However,congestioncanappear
attheinternaledgeoftheblockage,ortimingproblemsmightoccur.The
worstcasescenariohappenswhenthepinsofonemacroareplacedinthesame
channelwherethepinsofanothermacrooppositeareplaced.Anotherproblem
isthatportsarelocatedattheendofthechannel.
Inadenselypackeddesign,alargenumberofcompleteblockagesmightcause
insufficientplacementareatoplacethedesign.

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ChannelPlanning
Createchannelswideenoughtoaccommodateallrouting,powerrings(ifany),
andthebusexpansionareaoutsidethemacrospinssothatnetscangoacross
thechannelstowardtheinternalpartofablock.However,useonlynecessary
widthforchannelroutingtosavearea.
MacroTreatment
Macroplacement(ororientation)shouldminimizetheinterconnectbetween
thepinsofmacrosandinternalblock.Thesamemacrosarefacingthepins
iftheyareconnectedtothesamebus,thepinsshouldalignrespectivelyeven
ifthepinsarenotorganizedvisually.Ifthemacrosareconnectedtodifferent
busesandmorethantworoutinglayersareavailable,pinalignmentisstill
recommended.
PowerGrid(Mesh)
Apowergridsuppliespowertoallchipcomponents(transistors).IRdrop
(voltagedrop)alongthepowersupplylinecancausethebasiccomponentsof
thedesign,thetransistors,tofailormalfunction.Ifadesignhasapad
ringcontainingallthepadsincludingpowerpadsthatarelocatedatthechip
boundaries,someareas(especiallyinthecenterornearareasthataremasked
frompowerrouting)mightnotgetthevoltagelevelneededtofunctionproperly.
Toavoidthisproblem,youcandesignaveryrobustgridtoencompassthechip.
WhenyoucannotmeetthegoalsofIRdropusingasinglelayerperdirectionor
thetopmetalwiththesmallestresistance,youcandesignagridwithtwoor
morelayersperdirection.However,anextensiveuseofroutingresourcesor
placingmetalinanondefaultpowergridmetaldirectionmightcreateadesign
thatisnotroutable.
AnalyzingthePowerPlan
Powerplanningisderivedfromchiplevelfloorplanning,soyourinitial
workshouldbedoneatthepowerplanstage.Analyzingthepowerplan
beforegettingtotheblocklevelcanbeagoodstartingpoint.Tools
suchasJupiterXTpowernetworkanalysisandAstroRailshouldbeusedto
verifythatagridisrobustenoughbutdoesnotwasteroutingresources.
UseJupiterXTpowernetworksynthesisandpowerpadsynthesistohelpyou
createamoreefficientpowerplan.
NonoptimizedTrackUse
Inmanycases,apowergridisspreadevenlyacrossthewholechipregardless
ofthebasicroutingpitchandroutinggridlocation.Anevenlyspreadpower
gridcanresultinlosingroutingresourcesnearthepowergrid.Toavoid
losingroutingresources,adjustboththepowerstrapwidthanddistancebetween
strapsalongthegrid.
DifferentWidthsInsideaSpecificBlock
Becauseapowerstrapwidthisspecifiedforthepowersupplyoftheentire
chipregardlessofthedistancefromapowerpad,thepowerstraphasthesame
widthallalong.Forhighroutingdemand,considerthinningorremovingafew
powerstraps(afterconsultingwithyourpowerplandesigner)andanalyzethe
results.IfthesolutionadverselyaffectstheIRdropoftheentirechipbut
theblocklooksfine,addingapowerringaroundthisblockmighthelp.
NondefaultViaRules
Thedefaultbehaviorofapowergridroutingisspecifiedbyputtingavia
arrayatthecrossingpoint.Everypassbetweentwodifferentlayerswiththe
samedirectioncreatesastackvia.Astackviaisasmallmetalareagenerated
fromalayerdedicatedtoadifferentdirection.Forexample,ifmetal#3and
metal#5arededicatedtoverticaldirection,andmetal#4andmetal#6are
dedicatedtohorizontaldirection,astackviabetweenmetal#3andmetal#5uses
metal#4.Inthiscase,theamountandshapeofviasshouldbelimited.Thiscan
beachievedbyputtingmoreeffortinthestripesdesignstep;thatis,keepthe
verticallayerlowerthanthehorizontaltoavoidunconnectedpowerstraps.
UseseparatestepsforviasbyselectingtheaxgCreatePrerouteContactsmenuand
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theaxgPrerouteStandardCellsmenuAdvanceViaRulesdialogbox.
PortLocationChanges
Thissectiondescribessomecongestionproblemsdrivenfromportlocations.
Forthepurposesofthisdocument,itisassumedthatyoudon'thavefullcontrol
overportlocationsandsidesattheblocklevel.
Inputsvs.Outputs
Portlocationhashugeimpactonplacement.Manyplacementapproaches(including
wirelengthandtiming)placebothinputcellsandportisolationcellsand
connectthemclosetoinputports.Placingisolationcellsclosetotheports
oftenoccursinthecasesofveryhighinputdelayversusclockrates.Output
portshavefewerportlocationissues.Fromatimingpointofview,ifthere
arestrongcellsinthelibrarythatcansupportDRCandoutputdelaysversus
clockrates,outputportscanbewithinacertaindistancefromtheports.
Manyportsthatarecondensedwithinasmallportionofthedesignareamight
conflictwithreasonablecellplacement,especiallythosecellswithdirect
connectionstoports.Thesolutionforthisissueistospreadouttheinput
portsasmuchaspossible.
RoutingBottlenecks
Anotherissueistheroutingbottleneckwhereyouhavemanyroutingsegments
withalimitedamountoflayersandyoutrytofollowbackenddesignrulesto
changethedirectionofportswithminimumspacingrules.Onesolutionfor
thisissueistospreadouttheseportsasmuchaspossible.Anothersolution
istouseplacementsoftblockagesneartheports.Usesoftblockagesinsteadof
hardblockagestoavoidtimingandDRCissues.Inverydifficultcases,usea
progressiveblockageapproach.
LimitedChannels
Alimitedchannelistheuseofportshiddenbehindhardmacros.Whenachannel
(boththeareabetweenafewmacrosandthedistancebetweenmacrosanddesign
borders)istoosmall,eventotheamountofroutingthatshouldpassthrough
it,itiscalledalimitedchannel.Alimitedchannelmightbeanissuewhere
therearealimitednumberoflayers,especiallyintechnologieswherethere
arefewerroutinglayersovermacros.Inthiscase,noblockagecanbeused,
sothechannelshouldberesized.Thisphenomenacanbedetectedatthedesign
planningstage.
BlockLevelFloorplanAdjustments
Youcanusethefollowingblocklevelfloorplanadjustmentstoimprovecongestion.
LocalUtilization
OnemethodyoucanusewithICCompilertoimprovecongestionislocalutilization.
Notethatcongestionandutilizationaretwodifferentdesignchallenges.After
locatingabottleneck,youcancontroltheamountofcellsbydefininglocal
utilizationbypercentage.
Usethefollowingcommandtoimplementlocalutilization:
set_congestion_optionscoordinate{}max_util0.X
Thissolutioncanbeusedinseveralplacesinablock,andyoucanspecify
adifferentnumberforeachplace.Arestrictiontothiscommandisthat
themax_utilvalueshouldbelessthan1.0butnottoolow.Insomecases,
youmightfindthatthecongestedareafloatstonearbyareas.Therefore,
usinglocalutilizationtoimprovecongestioncanleadtofurtheradjustments.
NondefaultDirectionRouting
Thissolutionusesanondefaultroutingdirectionwithrouteguides.Itmight
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behelpfultoallowroutingovermacrostosolvemassivedetourrouting.Some
macromanufacturersallowyoutoroutewithmetalsthatarehigherthanmetal#5
overcertainmacros.Thiscansometimesbedoneafterfittingthedesignrules
oflowermetals.Withinsomedesigns,thismetalroutingdirectionisopposite
tothedesireddirection.Byusingrouteguides,youcansolvesomeofthe
congestionproblemsusingcreate_route_guideorchooseFlourplan>Create
RouteGuideintheGUI.
create_route_guideswitch_preferred_direction
BoundingorGroupingSubblocksWithoutCongestionOptions
Sometimesyoumightwanttoputspecificsubdesignsorsubblockseither
togetherorwithinaspecificplaceinadesignprimarilytosolvetiming
issues.Youcandothisbygeneratingbounds,whichcanbeusedtosolve
congestionissuesinothercases.Thecommandusedtoimplementthis
approachisasfollows.(Usedifferentnumbersforeachsubblock.)

create_boundsnamebound1coordinate{}efforthigh|ultratype\
hard[get_cellscell_list1]
create_boundsnamebound2coordinate{}efforthigh|ultratype\
hard[get_cellscell_list2]

Thesolutionhasonerestrictionthattoomanyboundscanslowdownthe
placementstage.Theallocatedareashouldfittheexpectedcellarea.Ifthe
areaistoolarge,movingothercellsintothespacesinsidetheboundcauses
congestionagain.Iftheareaistoosmall,thisapproachwon'tbehonored.
Afterinspection,thisstepshouldbedonecarefully.Whenthebalanceisbroken,
resultscanbecomemuchworse.
CombiningBoundingSubblocksWithLocalUtilization(WithCongestionOptions)
Whenyouinspectlocalutilizationusage,determineiftheplacercanputa
groupofcellstogetherespeciallyfortiming.Ifthereasonablelocationof
agroupofcellshasalocalutilizationrestrictionandtheplacerputsthe
groupsomewhereelse,theeffortisnotsuccessfulbecausecongestion
remainsandtimingisadverselyimpacted.
Youcanforcecellstogroupinaspecificlocationandtoutilizelocally
bycombiningaboundingcommandforthisgroupofcellstogether.Thecommands
toimplementthisapproachareasfollows:

create_boundsnamebound1coordinate{X1Y1X2Y2}efforthigh\
typehard[get_cellscell_list1]
set_congestion_optionscoordinate{X1Y1X2Y2}max_util0.X
create_placementtiming(orrefine_placement)
Therestrictionforthissolutionisthattoomanyboundscanslowdownthe
placementstage.Theallocatedareashouldfitintotheexpectedcellareafor
thisutilization.Iftheareaistoobig,othercellscanjumpintothespaces
insidetheboundtocausecongestionagain.Iftheareaistoosmall,the
utilizationwon'tbehonored.Oninspection,determineifthegroupingis
timingbased.Cellsthatgetstuckinthecornerorsideviolatethemax_util
valuewhilesomeoftheboundingarearemainsempty.
StrategicKeepouts

Thissolutionputsplacementblockagesinareaswithveryhighcongestion.
Afterallocatingthebottleneck,youcancontroltheamountofcellsbydefining
thestrategickeepouts.Bydefault,ICCompilerhassomekeepoutareasaround
macrosespeciallyformacropins.Youcandefinestrategickeepoutsmanually
orcreatescriptinICCompiler.Thescripttakesthecongestedregionsbased
onthethresholdyoudefineandgeneratesblockagesoverthehighlycongested
area.Insomecases,iftheutilizationislimited,theoptimizationmight
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latertrytoputthecellsinotherplacessothatthecongestioncanmove
toalessrestrictedarea.
AnExampleofUsingScripttoGenerateStrategicKeepouts
#CustomerControl#
setrun_num1
setcongestion_threshold1.3
setcon_placement_typehard
#ScriptBody
redirectvarcongested_area{get_congested_regionsthreshold\
$congestion_threshold}
setcongestion_vector[split[lindex$congested_area[expr[llength\
$congested_area]2]]","]
foreachi$congestion_vector{\
setsbn"[stringtrim[lindex[split$i""]0]\{][lindex\
[split$i""]1]";\
create_placement_blockagetype$con_placement_typecoordinat\
[list[stringtrim[lindex[split$i""]0]\{]\
[lindex[split$i""]1][lindex[split$i""]2]\
[stringtrim[lindex[split$i""]3]\}]]\
nameconblckg$run_num$sbn
}
ForMoreInformation:
SeealsotheSNUGIsrael2006userpaper(C4):"TheCongestionDragonCan
beDefeated.FightingCongestionTechniqueswithPhysicalCompiler."

2015Synopsys,Inc.AllRightsReserved.

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