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Library Ieee Use Ieee - STD - Logic - 1164.all : Zero One Two Three

This document describes an entity with 5 inputs (a, b, c, d, e) and one output (data_bus). It uses multiplexers and tri-state buffers to selectively enable the inputs onto the output bus based on the control signals y2y1 and y0. When enabled, an input is driven on the bus, otherwise the buffer is high impedance to allow other enabled inputs to drive the bus.

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Ilfiyantri Intyas
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70 views17 pages

Library Ieee Use Ieee - STD - Logic - 1164.all : Zero One Two Three

This document describes an entity with 5 inputs (a, b, c, d, e) and one output (data_bus). It uses multiplexers and tri-state buffers to selectively enable the inputs onto the output bus based on the control signals y2y1 and y0. When enabled, an input is driven on the bus, otherwise the buffer is high impedance to allow other enabled inputs to drive the bus.

Uploaded by

Ilfiyantri Intyas
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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zero

rst

library ieee;
use ieee.std_logic_1164.all;

entity soal1 is
port(
clk : in std_logic;
rst : in std_logic;
d

: in std_logic;

: out std_logic

);
end soal1;

architecture beh_FSM of soal1 is

one

two

three

type statefsm is (zero, one, two, three);


signal statekini : statefsm;
signal stateberikut : statefsm;

begin
stateInit: process(rst,clk)
begin
if rst = '1' then
statekini <= zero;
elsif rising_edge(clk) then
statekini <= stateberikut;
end if;
end process;

stateRun: process (statekini, d)


begin
case statekini is
when zero =>
q <= '0';
if d = '1' then
stateberikut <= one;
else
stateberikut <= zero;
end if;

when one =>

q <= '0';
if d = '1' then
stateberikut <= two;
else
stateberikut <= zero;
end if;

when two =>


q <= '0';
if d = '1' then
stateberikut <= three;
else
stateberikut <= zero;
end if;

when three =>


q <= '0';
if d = '0' then
stateberikut <= three;
else
stateberikut <= zero;
end if;

when others =>


stateberikut <= zero;

end case;
end process;
end beh_FSM;

add_imm

outmux1[15..0]
Add0

SEL
16' h2000 --

imm[15..0]

DATAA

outmux3[15..0]

A [1 5..0 ]

OUT0

DATAB

B [1 5..0 ]

DATAB
ADDER

MUX21

sel_a

outmux2[15..0]

outFF[15..0]

SEL
DATAA

PRE
OUT0

Q
16' h0000 --

ENA
MUX21

CLR

SEL
DATAA

a[15..0]

DATAB

OUT0

MUX21

outor
sel_imm
clk
reset_n
en

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity soal2 is
port (
clk

: in std_logic;

reset_n

: in std_logic;

en

: in std_logic;

add_imm

: in std_logic;

imm

: in std_logic_vector(15 downto 0);

: in std_logic_vector(15 downto 0);

addr[31..0]

sel_a : in std_logic;
sel_imm

: in std_logic;

addr : out std_logic_vector(31 downto 0)


);
end soal2;

architecture beh_PC of soal2 is


constant imm_add : std_logic_vector(15 downto 0) := x"0004";
constant FFadd : std_logic_vector(15 downto 0):= x"0000";
signal outmux1 : std_logic_vector(15 downto 0);
signal outmux2 : std_logic_vector(15 downto 0);
signal outmux3 : std_logic_vector(15 downto 0);
signal outadder : std_logic_vector(15 downto 0);
signal outor : std_logic;
signal outFF : std_logic_vector(15 downto 0);

begin
mux1:process(add_imm,imm)
begin
if add_imm ='1' then
outmux1 <= imm;
else
outmux1 <= imm_add;
end if;
end process;

mux2:process(imm, a, sel_a)
begin
if sel_a ='1' then
outmux2 <= a;
else
outmux2 <= imm;
end if;
end process;

mux3: process(outor,outmux2,outadder)
begin
if outor = '1' then
outmux3 <= outmux2;
else
outmux3 <= outadder;
end if;
end process;

-- adder:
outadder <= outmux1 + outFF;

-- logic_or:
outor <= sel_a or sel_imm;

-- output
addr <= outFF & FFadd;

Flipflop: process(reset_n,clk,en, outmux3)


begin
if reset_n = '0' then
outFF <= (others => '0');
elsif rising_edge(clk) then
if en = '1' then
outFF <= outmux3;
end if;
end if;
end process;

end beh_PC;

Mux0
outand[7]

SEL[7..0]

B[7..0]

FOUT[7..0]~reg0
PRE

DATA[255..0]

A[7..0]

OUT

Add0
A [7 ..0 ]

8' h01 --

CN[7..0]

B [7 ..0 ]

+
ADDER

outand[6]

MUX

Mux1

SEL[7..0]

DATA[255..0]

ENA
OUT

MUX

Mux2
outand[5]

SEL[7..0]

DATA[255..0]

OUT

MUX

Mux3
outand[4]

SEL[7..0]

DATA[255..0]

OUT

MUX

Mux4
outand[3]

SEL[7..0]

DATA[255..0]

OUT

MUX

Mux5
outand[2]

SEL[7..0]

DATA[255..0]

OUT

MUX

Mux6
outand[1]

SEL[7..0]

DATA[255..0]

OUT

MUX

Mux7
outand[0]

SEL[7..0]

OUT

CLR

FOUT[7..0]

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity soal3 is
port(
CN

: in std_logic_vector(7 downto 0);

: in std_logic_vector(7 downto 0);

: in std_logic_vector(7 downto 0);

clk

: in std_logic;

FOUT : out std_logic_vector(7 downto 0)


);
end soal3;

architecture beh_circuit of soal3 is


signal F : std_logic_vector(7 downto 0);
signal outand : std_logic_vector(7 downto 0);
begin
--mux4to1
with CN select
F <= A when x"00",
not A when x"01",
A + 1 when x"02",
outand when others;

-- logic and
outand <= A and B;

flipflop:process(clk,F)
begin
if rising_edge(clk) then
FOUT <= F;
end if;
end process;

end beh_circuit;

Mux0

anb
a
b

0
0

SEL[1..0]

c
d

4' h6 --

DATA[3..0]

MUX

library ieee;
use ieee.std_logic_1164.all;

entity soal4 is
port(
a

: in std_logic;

: in std_logic;

: in std_logic;

OUT

: in std_logic;

: out std_logic

);
end soal4;

architecture beh_CSA of soal4 is


signal y

: std_logic;

signal ynd

: std_logic_vector(1 downto 0);

signal anb

: std_logic;

begin

anb <= a and b;


y <= '0' when c ='1' else
anb;

ynd <= y & d;

with ynd select


q <= '0' when "00",
'1' when "01",
'1' when "10",
'0' when others;

end beh_CSA;

soal no 4

Mux0

aorb
a
b

0
0

SEL[1..0]

c
d

4' h6 --

DATA[3..0]

MUX

library ieee;
use ieee.std_logic_1164.all;

entity soal4 is
port(
a

: in std_logic;

: in std_logic;

: in std_logic;

: in std_logic;

: out std_logic

);
end soal4;

architecture beh_CSA of soal4 is


signal y

: std_logic;

OUT

signal ynd : std_logic_vector(1 downto 0);


signal aorb : std_logic;
begin

aorb <= a or b;
y <= '0' when c ='1' else
aorb;

ynd <= y & d;

with ynd select


q <= '0' when "00",
'1' when "01",
'1' when "10",
'0' when others;

end beh_CSA;

soal 5

Mux3
y2y1[1..0]

SEL[1..0]
4' h8 --

DATA[3..0]

0
OUT

reg_e[7]~7

enable_e
reg_c[7]~7
MUX

IO_BUF (TRI)

reg_e[6]~6

Mux2
IO_BUF (TRI)
SEL[1..0]
4' h2 --

DATA[3..0]

IO_BUF (TRI)
OUT

reg_e[5]~5
reg_c[6]~6

MUX
IO_BUF (TRI)
IO_BUF (TRI)

reg_e[4]~4

reg_c[5]~5
IO_BUF (TRI)
IO_BUF (TRI)

reg_e[3]~3

reg_c[4]~4
IO_BUF (TRI)
IO_BUF (TRI)

reg_e[2]~2

reg_c[3]~3
IO_BUF (TRI)
IO_BUF (TRI)

reg_e[1]~1

reg_c[2]~2
IO_BUF (TRI)
IO_BUF (TRI)

reg_e[0]~0

reg_d[7]~7

e[7..0]
y0

IO_BUF (TRI)
0
1

enable_d
reg_c[1]~1
c[7..0]

IO_BUF (TRI)

reg_d[6]~6
IO_BUF (TRI)

reg_c[0]~0
Mux1

IO_BUF (TRI)

reg_d[5]~5
IO_BUF (TRI)

SEL[1..0]
4' h4 --

DATA[3..0]

OUT

reg_b[7]~7

IO_BUF (TRI)

reg_d[4]~4
IO_BUF (TRI)

MUX

reg_b[6]~6

IO_BUF (TRI)

reg_d[3]~3
IO_BUF (TRI)

reg_b[5]~5

IO_BUF (TRI)

reg_d[2]~2
IO_BUF (TRI)

reg_b[4]~4

IO_BUF (TRI)

reg_d[1]~1
IO_BUF (TRI)

reg_b[3]~3

IO_BUF (TRI)

reg_d[0]~0
IO_BUF (TRI)

reg_b[2]~2

IO_BUF (TRI)

IO_BUF (TRI)

reg_b[1]~1
b[7..0]
IO_BUF (TRI)

reg_b[0]~0
Mux0
IO_BUF (TRI)
SEL[1..0]
4' h8 --

DATA[3..0]

MUX

OUT

reg_a[7]~7

IO_BUF (TRI)

reg_a[6]~6

IO_BUF (TRI)

reg_a[5]~5

IO_BUF (TRI)

reg_a[4]~4

IO_BUF (TRI)

reg_a[3]~3

IO_BUF (TRI)

reg_a[2]~2

IO_BUF (TRI)

data_bus[39..0]

library ieee;
use ieee.std_logic_1164.all;

entity soal5 is
port(
a

: in std_logic_vector(7 downto 0);

: in std_logic_vector(7 downto 0);

: in std_logic_vector(7 downto 0);

: in std_logic_vector(7 downto 0);

: in std_logic_vector(7 downto 0);

y2y1: in std_logic_vector(1 downto 0);


y0

: in std_logic;

data_bus : out std_logic_vector(39 downto 0)


);
end soal5;

architecture beh_buff of soal5 is


signal enable_a : std_logic;
signal enable_b : std_logic;
signal enable_c : std_logic;
signal enable_d : std_logic;
signal enable_e : std_logic;
signal demux00 : std_logic;
signal reg_a

: std_logic_vector(7 downto 0);

signal reg_b

: std_logic_vector(7 downto 0);

signal reg_c

: std_logic_vector(7 downto 0);

signal reg_d

: std_logic_vector(7 downto 0);

signal reg_e

: std_logic_vector(7 downto 0);

begin
--demux1to4
with y2y1 select
enable_a <= '1' when "11",
'0' when others;
with y2y1 select
enable_b <= '1' when "10",
'0' when others;
with y2y1 select
enable_c <= '1' when "01",
'0' when others;
with y2y1 select
demux00 <= '1' when "11",
'0' when others;
--demux1to2
with y0 select
enable_d <= demux00 when '1',
'0' when others;
with y0 select
enable_e <= demux00 when '0',
'0' when others;

-- tri state buffer

reg_a <= a when enable_a = '1' else (others => 'Z');


reg_b <= b when enable_b = '1' else (others => 'Z');
reg_c <= c when enable_c = '1' else (others => 'Z');
reg_d <= d when enable_d = '1' else (others => 'Z');
reg_e <= e when enable_e = '1' else (others => 'Z');

data_bus <= reg_a & reg_b & reg_c & reg_d & reg_e;

end beh_buff;

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