DSD Lab Report

SUBMITTED BY AVINASH T(M130122EC) , JINESH K B(M130121EC)

DSD Lab Report

Table of Contents

MODULE I STRUCTURAL MODELING

1. HALF ADDER AND HALF SUBTRACTOR

2. FULL ADDER AND FULL SUBTRACTOR
3.4 BIT BINARY ADDER
4. SYNCHRONOUS COUNTER (UP, DOWN, UP/DOWN )

3
8
15
18

MODULE II DATA FLOW MODELING

27

1. HALF ADDER
2. FULL ADDER
3. COMPARATOR (4 BIT)
4. SHIFT REGISTER 16 BIT AND 64 BIT)
5. MULTIPLEXER WITH TRISTATING
6. DECODER WITH TRISTATING)

28
31
34
37
42
45

MODULE III BEHAVIORAL MODELING

48

1. 4 BIT BINARY COUNTER

2. UP/DOWN DECADE COUNTER
3. BCD SUBTRACTOR AND ADDER
4. D FLIP FLOP
5. T FLIP FLOP
6. JK FLIP FLOP

49
52
55
60
63
66

DSD Lab Report

MODULE I :STRUCTURAL MODELING

DSD Lab Report

1.HALF ADDER AND HALF SUBTRACTER

AIM
a) To design half adder in structural model.
b) To design half subtractor in structural model.

THEORY
a)

Half adder is designed using one 2 input XOR gate and one 2 input AND gate. The design equation is
obtained by solving K-map and is given by
SUM = A B
CARRY = AB

b) Half subtractor is designed using one 2 input XOR gate, one 2 input and gate and one NOT gate. The design
equation is given by
DIFFERENCE = A B
BORROW = A

TRUTH TABLE

A
0
0
1
1

HALF ADDER
INPUT
OUTPUT
B
SUM
CARRY
0
0
0
1
1
0
0
1
0
1
0
1

A
0
0
1
1

HALF SUBTRACTOR
INPUT
OUTPUT
B
DIFFERENCE BORROW
0
0
0
1
1
1
0
1
0
1
0
0

SCHEMATIC DIAGRAM

DSD Lab Report

PROGRAM
a. HALF ADDER
VHDL CODE :
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY HALF_ADDER IS
PORT ( A,B : IN STD_LOGIC;
SUM,CARRY : OUT STD_LOGIC);
END HALF_ADDER;
ARCHITECTURE BEHAVIORAL OF HALF_ADDER IS
COMPONENT AND_GATE IS
PORT ( A,B : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END COMPONENT;
COMPONENT XOR_GATE IS
PORT ( A,B : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END COMPONENT;

BEGIN
A0: XOR_GATE PORT MAP(A,B,SUM);
A1: AND_GATE PORT MAP (A,B,CARRY);
END BEHAVIORAL;

TEST BENCH
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TB_HALF_ADDER IS
END TB_HALF_ADDER;
ARCHITECTURE BEHAVIOR OF TB_HALF_ADDER IS
COMPONENT HALF_ADDER
PORT(A : IN STD_LOGIC;
B : IN STD_LOGIC;
SUM : OUT STD_LOGIC;
CARRY : OUT STD_LOGIC );
END COMPONENT;
SIGNAL A : STD_LOGIC := '0';
SIGNAL B : STD_LOGIC := '0';
SIGNAL SUM : STD_LOGIC;
SIGNAL CARRY : STD_LOGIC;

DSD Lab Report

BEGIN
UUT: HALF_ADDER PORT MAP (
A => A,
B => B,
SUM => SUM,
CARRY => CARRY );
STIM_PROC: PROCESS
BEGIN
A <= '0','1' AFTER 100 NS,'0' AFTER 200 NS;
B <= '0','1' AFTER 50 NS,'0' AFTER 100 NS,'1' AFTER 150 NS,'0' AFTER 200 NS;
WAIT;
END PROCESS;
END;

OUTPUT

b. HALF SUBTRACTOR
VHDL CODE:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY HALF_SUBTRACTOR IS
PORT ( A,B : IN STD_LOGIC;
DIFFERENCE,BORROW : OUT STD_LOGIC);
END HALF_SUBTRACTOR;
ARCHITECTURE BEHAVIORAL OF HALF_SUBTRACTOR IS
COMPONENT NOT_GATE IS
PORT ( A : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END COMPONENT;
COMPONENT AND_GATE IS

DSD Lab Report

PORT ( A,B : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END COMPONENT;
COMPONENT XOR_GATE IS
PORT ( A,B : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END COMPONENT;
SIGNAL BBAR : STD_LOGIC;
BEGIN
A0 : NOT_GATE PORT MAP(B,BBAR);
A1 : AND_GATE PORT MAP(A,BBAR,BORROW);
A2 : XOR_GATE PORT MAP(A,B,DIFFERENCE);
END BEHAVIORAL;

TEST BENCH
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TB_HALF_SUBTRACTOR IS
END TB_HALF_SUBTRACTOR;
ARCHITECTURE BEHAVIOR OF TB_HALF_SUBTRACTOR IS
COMPONENT HALF_SUBTRACTOR
PORT(
A : IN STD_LOGIC;
B : IN STD_LOGIC;
DIFFERENCE : OUT STD_LOGIC;
BORROW : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL A : STD_LOGIC := '0';
SIGNAL B : STD_LOGIC := '0';
SIGNAL DIFFERENCE : STD_LOGIC;
SIGNAL BORROW : STD_LOGIC;
BEGIN
UUT: HALF_SUBTRACTOR PORT MAP (
A => A,
B => B,
DIFFERENCE => DIFFERENCE,
BORROW => BORROW );
STIM_PROC: PROCESS
BEGIN
A <= '0','1' AFTER 100 NS,'0' AFTER 200 NS;
B <= '0','1' AFTER 50 NS,'0' AFTER 100 NS,'1' AFTER 150 NS,'0' AFTER 200 NS;
WAIT;
END PROCESS;
END;

DSD Lab Report

OUTPUT

COMPNENTS USED
XOR_GATE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

AND_GATE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

NOTGATE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY XOR_GATE IS
PORT ( A,B : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END AND_GATE;

ENTITY AND_GATE IS
PORT ( A,B : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END AND_GATE;

ENTITY NOTGATE IS
PORT ( A : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END NOTGATE;

ARCHITECTURE BEHAVIORAL
OF XOR_GATE IS

ARCHITECTURE BEHAVIORAL
OF AND_GATE IS

ARCHITECTURE BEHAVIORAL
OF NOTGATE IS

BEGIN

BEGIN

BEGIN

Y <= A XOR B;

Y <= A AND B;

END BEHAVIORAL;

END BEHAVIORAL;

Y <= NOT A ;
END BEHAVIORAL;

RESULT
Implemented half adder and half subtractor in structural model and verified the outputs.

DSD Lab Report

2.FULL ADDER AND FULL SUBTRACTOR

AIM
a. To design full adder using structural model.
b. To design full subtractor using structural model
THEORY
a. A full adder circuit is an arithmetic circuit block that can be used to add three bits to produce
a SUM and a CARRY output.
SUM= A B Cin
CARRY= A B +Cin B+Cin A
Here full adder is realised using two half adders and an OR gate.
b. A full subtractor circuit is an arithmetic circuit block that can be used to subtract three bits to
produce a DIFFERENCE and a BORROW output

DIFFERENCE= A B Bin
BORROW =

Here full subtractor is realised using two half ubtractors and an OR gate.

TRUTH TABLE
FULL ADDER
INPUT
A

Cin

FULL SUBTRACTOR
INPUT
OUTPUT

OUTPUT
Sum

Carry

Bin

Diff.

Borrow

DSD Lab Report

SCHEMATIC DIAGRAM
a.

b.

Full adder

Full subtractor

DSD Lab Report

PROGRAM
a. FULL ADDER
VHDL CODE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FULLADDER IS
PORT ( A,B,CIN : IN STD_LOGIC;
SUM,CARRY : OUT STD_LOGIC);
END FULLADDER;
ARCHITECTURE BEHAVIORAL OF FULLADDER IS
COMPONENT HALF_ADDER IS
PORT ( A,B : IN STD_LOGIC;
SUM,CARRY : OUT STD_LOGIC);
END COMPONENT;
COMPONENT ORGATE IS
PORT ( A,B : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END COMPONENT;
SIGNAL S1,S2,S3 :STD_LOGIC;
BEGIN
HA0 : COMPONENT HALF_ADDER PORT MAP(A,B,S1,S2);
HA1 : COMPONENT HALF_ADDER PORT MAP (S1,CIN,SUM,S3);
OR0 : COMPONENT ORGATE PORT MAP(S2,S3,CARRY);
END BEHAVIORAL;
TEST BENCH
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TB_FULLADDER IS
END TB_FULLADDER;
ARCHITECTURE BEHAVIOR OF TB_FULLADDER IS
COMPONENT FULLADDER
PORT( A : IN STD_LOGIC;
B : IN STD_LOGIC;
CIN : IN STD_LOGIC;
SUM : OUT STD_LOGIC;
CARRY : OUT STD_LOGIC );
END COMPONENT;

10

DSD Lab Report

SIGNAL A : STD_LOGIC := '0';
SIGNAL B : STD_LOGIC := '0';
SIGNAL CIN : STD_LOGIC := '0';
SIGNAL SUM : STD_LOGIC;
SIGNAL CARRY : STD_LOGIC;
BEGIN
UUT: FULLADDER PORT MAP (
A => A,
B => B,
CIN => CIN,
SUM => SUM,
CARRY => CARRY );
STIM_PROC: PROCESS
BEGIN
A<='0','1' AFTER 160 NS,'0' AFTER 320 NS;
B<='0','1' AFTER 80 NS,'0' AFTER 160 NS,'1' AFTER 240 NS,'0' AFTER 320 NS;
CIN<='0','1' AFTER 40 NS,'0' AFTER 80 NS,'1' AFTER 120 NS,'0' AFTER 160 NS,'1' AFTER 200
NS,'0' AFTER 240 NS,'1' AFTER 280NS,'0' AFTER 320 NS;
WAIT;
END PROCESS;
END;

OUTPUT

b. FULL SUBTRACTOR
VHDL CODE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FULLSUBTRACTOR IS
PORT ( A,B,BIN : IN STD_LOGIC;
DIFFERENCE,BORROW : OUT STD_LOGIC);
END FULLSUBTRACTOR;
ARCHITECTURE BEHAVIORAL OF FULLSUBTRACTOR IS

11

DSD Lab Report

COMPONENT HALF_SUBTRACTOR IS
PORT ( A,B : IN STD_LOGIC;
DIFFERENCE,BORROW : OUT STD_LOGIC);
END COMPONENT;
COMPONENT ORGATE IS
PORT ( A,B : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END COMPONENT;
SIGNAL S1,S2,S3 :STD_LOGIC;
BEGIN
HS0 : COMPONENT HALF_SUBTRACTOR PORT MAP(A,B,S1,S2);
HS1 : COMPONENT HALF_SUBTRACTOR PORT MAP (S1,BIN,DIFFERENCE,S3);
OR0 : COMPONENT ORGATE PORT MAP(S2,S3,BORROW);
END BEHAVIORAL;

TEST BENCH
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TB_FULLSUBTRACTOR IS
END TB_FULLSUBTRACTOR;
ARCHITECTURE BEHAVIOR OF TB_FULLSUBTRACTOR IS
COMPONENT FULLSUBTRACTOR
PORT(
A : IN STD_LOGIC;
B : IN STD_LOGIC;
BIN : IN STD_LOGIC;
DIFFERENCE : OUT STD_LOGIC;
BORROW : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL A : STD_LOGIC := '0';
SIGNAL B : STD_LOGIC := '0';
SIGNAL BIN : STD_LOGIC := '0';
SIGNAL DIFFERENCE : STD_LOGIC;
SIGNAL BORROW : STD_LOGIC;

BEGIN
UUT: FULLSUBTRACTOR PORT MAP (
A => A,

12

DSD Lab Report

B => B,
BIN => BIN,
DIFFERENCE => DIFFERENCE,
BORROW => BORROW );
STIM_PROC: PROCESS
BEGIN
A<='0','1' AFTER 160 NS,'0' AFTER 320 NS;
B<='0','1' AFTER 80 NS,'0' AFTER 160 NS,'1' AFTER 240 NS,'0' AFTER 320 NS;
BIN<='0','1' AFTER 40 NS,'0' AFTER 80 NS,'1' AFTER 120 NS,'0' AFTER 160 NS,'1' AFTER 200
NS,'0' AFTER 240 NS,'1' AFTER 280 NS,'0' AFTER 320 NS;
WAIT;
END PROCESS;
END;

OUTPUT

COMPONENTS USED
1. HALF_ADDER
2. HALF_SUBTRACTOR
3. OR_GATE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY OR_GATE IS
PORT ( A : IN STD_LOGIC;
B : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END OR_GATE;
ARCHITECTURE BEHAVIORAL OF OR_GATE IS
BEGIN
Y <= A OR B ;
END BEHAVIORAL;

13

DSD Lab Report

RESULT
Implemented full adder and full subtractor in structural model and verified the outputs.

14

DSD Lab Report

3. 4 BIT BINARY ADDER

AIM To design a 4 bit binary adder in structural model.
THEORY
A four bit binary adder is implemented using four full adders cascaded in parallel such that carry out of each full
adder is the carry in of succeeding full adder.Thus each full adder will add one bit of both input along with the carry of
previous bit to give a four bit sum and one bit carry out.

SCHEMATIC DIAGRAM

VHDL CODE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FOUR_BIT_BINARY_ADDER IS
PORT ( A,B : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
CIN : IN STD_LOGIC;
SUM : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
COUT : OUT STD_LOGIC);
END FOUR_BIT_BINARY_ADDER;
ARCHITECTURE BEHAVIORAL OF FOUR_BIT_BINARY_ADDER IS
COMPONENT FULLADDER IS
PORT ( A,B,CIN : IN STD_LOGIC;
SUM,CARRY : OUT STD_LOGIC);

15

DSD Lab Report

END COMPONENT;
SIGNAL S:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
FA0 : COMPONENT FULLADDER PORT MAP(A(0),B(0),CIN,SUM(0),S(0));
FA1 : COMPONENT FULLADDER PORT MAP (A(1),B(1),S(0),SUM(1),S(1));
FA2 : COMPONENT FULLADDER PORT MAP(A(2),B(2),S(1),SUM(2),S(2));
FA3 : COMPONENT FULLADDER PORT MAP (A(3),B(3),S(2),SUM(3),S(3));
COUT<= S(3);
END BEHAVIORAL;

TEST BENCH
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TB_ADDER IS
END TB_ADDER;
ARCHITECTURE BEHAVIOR OF TB_ADDER IS
COMPONENT FOUR_BIT_BINARY_ADDER
PORT(
A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CIN : IN STD_LOGIC;
SUM : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
COUT : OUT STD_LOGIC );
END COMPONENT;
SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL B : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL CIN : STD_LOGIC := '0';
SIGNAL SUM : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL COUT : STD_LOGIC;
BEGIN
UUT: FOUR_BIT_BINARY_ADDER PORT MAP (
A => A,
B => B,
CIN => CIN,
SUM => SUM,
COUT => COUT
);

STIM_PROC: PROCESS
BEGIN
A<="0110","0111" AFTER 40 NS,"0000" AFTER 80 NS;
B<="1001","1111" AFTER 40 NS,"0000" AFTER 80 NS;
CIN<='0';
WAIT;
END PROCESS;
END;

16

DSD Lab Report

OUTPUT

RESULT
Implemented 4 bit binary adder in structural model and verified the output.

17

DSD Lab Report

4. SYNCHRONOUS COUNTER(UP,DOWN,UP/DOWN)
AIM
i.
ii.
iii.

To design synchronous up counter using structural model.

To design synchronous down counter using structural model.
To design synchronous up/down counter using structural model.

THEORY
A 4 bit synchronous counter is designed using 4 T flip flops .the design equation for up and down counters are
given by
i.

SYNCHRONOUS UP COUNTER
T0 = 1
T 1 = Q0
T2=Q0Q1
T3=Q0Q1Q2
Where T0 T1 T2 T3 are the inputs of stage 0 to 3 and Q0 Q1 Q2 are the outputs of respective stages .
To implement this in structural mode it requires 4 T flipflops and 2 AND gates.

ii.

SYNCHRONOUS DOWN COUNTER

T0 = 1
T1 = 0
T 2= 0 1
T 3= 0 1 2
Where T0 T1 T2 T3 are the inputs of stage 0 to 3 and Q0 Q1 Q2 are the outputs of respective stages .
To implement this in structural mode it requires 4 T flipflops and 2 AND gates.

iii.

SYNCHRONOUS UP/DOWN COUNTER

This circuit consist of an additional input mode to select whether up or down counter.design equation is given by
T0 = 1
T1 =Q0.MODE + 0.
T2= Q0Q1.MODE+ 0 1
T3= Q0Q1Q2.MODE+ 0 1 2 .
When mode=1,it works as up counter.
Mode=0,it works as down counter.

To implement this in structural mode it requires 4 T flipflops , 5 AND gates,3 OR gates and 1 NOT gate.

18

DSD Lab Report

SCHEMATIC DIAGRAM

VHDL CODE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SYN_UP IS
PORT ( CLK : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END SYN_UP;
ARCHITECTURE BEHAVIORAL OF SYN_UP IS
COMPONENT TFF PORT(T,CLK :IN STD_LOGIC;
Q,QBAR: OUT STD_LOGIC);
END COMPONENT;
COMPONENT AND_GATE IS
PORT ( A,B : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END COMPONENT;

SIGNAL S,N,M:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";

BEGIN
T0 : TFF PORT MAP('1',CLK,S(0),M(0));
T1 : TFF PORT MAP(N(0),CLK,S(1),M(1));
T2 : TFF PORT MAP(N(1),CLK,S(2),M(2));
T3 : TFF PORT MAP(N(2),CLK,S(3),M(3));
N(0)<= S(0);
A0: AND_GATE PORT MAP(S(0),S(1),N(1));
A1: AND_GATE PORT MAP (S(2),N(1),N(2));
Q<=S;
END BEHAVIORAL;

19

DSD Lab Report

TEST BENCH
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TB_UP_COUNTER IS
END TB_UP_COUNTER;
ARCHITECTURE BEHAVIOR OF TB_UP_COUNTER IS
COMPONENT SYN_UP
PORT(
CLK : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
SIGNAL CLK : STD_LOGIC := '0';
SIGNAL Q : STD_LOGIC_VECTOR(3 DOWNTO 0);
CONSTANT CLK_PERIOD : TIME := 10 NS;
BEGIN
UUT: SYN_UP PORT MAP (
CLK => CLK,
Q => Q
);
CLK_PROCESS :PROCESS
BEGIN
CLK <= '0';
WAIT FOR CLK_PERIOD/2;
CLK <= '1';
WAIT FOR CLK_PERIOD/2;
END PROCESS;
STIM_PROC: PROCESS
BEGIN
WAIT;
END PROCESS;
END;

OUTPUT

20

DSD Lab Report

SYNCHRONOUS DOWN COUNTER

SCHEMATIC DIAGRAM

VHDL CODE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SYN_DOWN IS
PORT ( CLK : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END SYN_DOWN;
ARCHITECTURE BEHAVIORAL OF SYN_DOWN IS
COMPONENT TFF PORT(T,CLK :IN STD_LOGIC;
Q,QBAR: OUT STD_LOGIC);
END COMPONENT;
COMPONENT AND_GATE IS
PORT ( A,B : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END COMPONENT;

SIGNAL S,N,M:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";

BEGIN
T0 : TFF PORT MAP('1',CLK,S(0),M(0));
T1 : TFF PORT MAP(N(0),CLK,S(1),M(1));
T2 : TFF PORT MAP(N(1),CLK,S(2),M(2));
T3 : TFF PORT MAP(N(2),CLK,S(3),M(3));

21

DSD Lab Report

N(0)<= M(0);
A0: AND_GATE PORT MAP(M(0),M(1),N(1));
A1: AND_GATE PORT MAP (M(2),N(1),N(2));
Q<=S;
END BEHAVIORAL;
TEST BENCH
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TB_DOWN_COUNTER IS
END TB_DOWN_COUNTER;
ARCHITECTURE BEHAVIOR OF TB_DOWN_COUNTER IS
COMPONENT SYN_DOWN
PORT(
CLK : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
SIGNAL CLK : STD_LOGIC := '0';
SIGNAL Q : STD_LOGIC_VECTOR(3 DOWNTO 0);
CONSTANT CLK_PERIOD : TIME := 10 NS;
BEGIN
UUT: SYN_DOWN PORT MAP (
CLK => CLK,
Q => Q
);
CLK_PROCESS :PROCESS
BEGIN
CLK <= '0';
WAIT FOR CLK_PERIOD/2;
CLK <= '1';
WAIT FOR CLK_PERIOD/2;
END PROCESS;
STIM_PROC: PROCESS
BEGIN
WAIT;
END PROCESS;
END;

22

DSD Lab Report

OUTPUT

iii. SYNCHRONOUS UP/DOWN COUNTER

SCHEMATIC DIAGRAM

VHDL CODE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SYN_UP_DOWN IS
PORT ( MODE,CLK : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END SYN_UP_DOWN;
ARCHITECTURE BEHAVIORAL OF SYN_UP_DOWN IS
COMPONENT TFF PORT(T,CLK :IN STD_LOGIC;
Q,QBAR: OUT STD_LOGIC);
END COMPONENT;
COMPONENT NOTGATE IS
PORT ( A : IN STD_LOGIC;
Y : OUT STD_LOGIC);

23

DSD Lab Report

END COMPONENT;
COMPONENT AND_GATE IS
PORT ( A,B : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END COMPONENT;
COMPONENT OR_GATE IS
PORT ( A,B : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END COMPONENT;
SIGNAL MODEBAR : STD_LOGIC;
SIGNAL S,N,M,U,D:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
BEGIN
N0 : NOTGATE PORT MAP(MODE,MODEBAR);
T0 : TFF PORT MAP('1',CLK,S(0),M(0));
T1 : TFF PORT MAP(N(0),CLK,S(1),M(1));
T2 : TFF PORT MAP(N(1),CLK,S(2),M(2));
T3 : TFF PORT MAP(N(2),CLK,S(3),M(3));
A0: AND_GATE PORT MAP(S(0),MODE,U(0));
A1: AND_GATE PORT MAP(U(0),S(1),U(1));
A2: AND_GATE PORT MAP (S(2),U(1),U(2));
A3: AND_GATE PORT MAP(MODEBAR,M(0),D(0));
A4: AND_GATE PORT MAP(D(0),M(1),D(1));
A5: AND_GATE PORT MAP (M(2),D(1),D(2));
O0:OR_GATE PORT MAP(D(0),U(0),N(0));
O1:OR_GATE PORT MAP(D(1),U(1),N(1));
O2:OR_GATE PORT MAP(D(2),U(2),N(2));
Q<=S;
END BEHAVIORAL;

TEST BENCH
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TB_UP_DOWN IS
END TB_ UP_DOWN;
ARCHITECTURE BEHAVIOR OF TB_ UP_DOWN IS
COMPONENT SYN_UP_DOWN
PORT(
MODE : IN STD_LOGIC;
CLK : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
SIGNAL MODE : STD_LOGIC := '0';
SIGNAL CLK : STD_LOGIC := '0';

24

DSD Lab Report

SIGNAL Q : STD_LOGIC_VECTOR(3 DOWNTO 0);

CONSTANT CLK_PERIOD : TIME := 10 NS;
BEGIN
UUT: SYN_UP_DOWN PORT MAP (
MODE => MODE,
CLK => CLK,
Q => Q
);
CLK_PROCESS :PROCESS
BEGIN
CLK <= '0';
WAIT FOR CLK_PERIOD/2;
CLK <= '1';
WAIT FOR CLK_PERIOD/2;
END PROCESS;
STIM_PROC: PROCESS
BEGIN
MODE<='1','0' AFTER 80 NS;
WAIT;
END PROCESS;
END;

OUTPUT

COMPONENTS USED
T FLIPFLOP
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

AND GATE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY TFF IS
PORT ( T,CLK : IN STD_LOGIC;
Q,QBAR : OUT STD_LOGIC);
END TFF;

ENTITY AND_GATE IS
PORT ( A,B : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END NOTGATE;

ARCHITECTURE BEHAVIORAL OF TFF IS

SIGNAL S: STD_LOGIC:='0';

ARCHITECTURE BEHAVIORAL OF AND_GATE IS

BEGIN

BEGIN
Q<=S;
QBAR<= NOT S;

PROCESS(A,B)

25

DSD Lab Report

PROCESS(CLK)
BEGIN
IF RISING_EDGE(CLK) THEN
IF(T='1') THEN
S<=NOT S;
ELSE S<=S;
END IF;

BEGIN
IF (A='1' AND B=1) THEN Y<='1' ;
ELSE Y<='0';
END IF;
END PROCESS;
END BEHAVIORAL;

END IF;
END PROCESS;
END BEHAVIORAL;
OR GATE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

NOT GATE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY OR_GATE IS
PORT ( A,B : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END NOTGATE;

ENTITY NOTGATE IS
PORT ( A : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END NOTGATE;

ARCHITECTURE BEHAVIORAL OF OR_GATE IS

ARCHITECTURE BEHAVIORAL OF NOTGATE IS

BEGIN

BEGIN

PROCESS(A,B)

PROCESS(A)

BEGIN
IF (A='0' AND B=0) THEN Y<='0' ;
ELSE Y<='1';
END IF;

BEGIN
IF A='1' THEN Y<='0' ;
ELSE Y<='1';
END IF;

END PROCESS;

END PROCESS;

END BEHAVIORAL;

END BEHAVIORAL;

RESULT
Implemented synchronous UP,DOWN and UP/DOWN counter in structural model and variefied the output.

26

DSD Lab Report

MODULE II :DATA FLOW MODELING

27

DSD Lab Report

1.HALF ADDER
AIM
To simulate a half adder in data flow model

THEORY
Half adder adds 2 bits and produce a sum and carry. The design equation is obtained by solving K-map and
is given by
SUM = A B
CARRY = AB

TRUTH TABLE
A

SUM

CARRY

SCHEMATIC DIAGRAM

28

DSD Lab Report

VHDL CODE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY HALF_ADDER IS
PORT ( A,B : IN STD_LOGIC;
SUM,CARRY : OUT STD_LOGIC);
END HALF_ADDER;
ARCHITECTURE DATAFLOW OF HALF_ADDER IS
BEGIN
SUM<= A XOR B;
CARRY<= A AND B;
END DATAFLOW;

TEST BENCH:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TB_HALF_ADDER IS
END TB_HALF_ADDER;
ARCHITECTURE DATAFLOW OF TB_HALF_ADDER IS
COMPONENT HALF_ADDER
PORT(
A : IN STD_LOGIC;
B : IN STD_LOGIC;
SUM : OUT STD_LOGIC;
CARRY : OUT STD_LOGIC
);
END COMPONENT;

SIGNAL A : STD_LOGIC := '0';

SIGNAL B : STD_LOGIC := '0';
SIGNAL SUM : STD_LOGIC;
SIGNAL CARRY : STD_LOGIC;
BEGIN
UUT: HALF_ADDER PORT MAP (
A => A,
B => B,
SUM => SUM,
CARRY => CARRY
);

29

DSD Lab Report

STIM_PROC: PROCESS
BEGIN
A<= '0','1' AFTER 20 NS;
B<= '0','1' AFTER 10 NS,'0' AFTER 25 NS;
WAIT;
END PROCESS;
END;

WAVE FORM

RESULT
Implemented half adder in data flow model and verified the result.

30

DSD Lab Report

2.FULL ADDER
AIM
To simulate a full adder in data flow model

THEORY
A full adder circuit is an arithmetic circuit block that can be used to add three bits to produce a SUM and a CARRY
output.

SUM= A B Cin
CARRY= A B +Cin B+Cin A
TRUTH TABLE
A

Cin

Sum

Cout

SCEMATIC DIAGRAM

31

DSD Lab Report

VHDL CODE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FULL_ADDER IS
PORT ( A,B,CIN : IN STD_LOGIC;
SUM,COUT : OUT STD_LOGIC);
END FULL_ADDER;
ARCHITECTUR DATAFLOW OF FULL_ADDER IS
BEGIN
SUM<= (A XOR B) XOR CIN;
COUT<= (A AND B) OR (B AND CIN) OR (A AND CIN);
END DATAFLOW;

TEST BENCH
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TB_FULL_ADDER IS
END TB_FULL_ADDER;
ARCHITECTURE DATAFLOW OF TB_FULL_ADDER IS
COMPONENT FULL_ADDER
PORT(
A : IN STD_LOGIC;
B : IN STD_LOGIC;
CIN : IN STD_LOGIC;
SUM : OUT STD_LOGIC;
COUT : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL A : STD_LOGIC := '0';
SIGNAL B : STD_LOGIC := '0';
SIGNAL CIN : STD_LOGIC := '0';
SIGNAL SUM : STD_LOGIC;
SIGNAL COUT : STD_LOGIC;
BEGIN
UUT: FULL_ADDER PORT MAP (
A => A,
B => B,
CIN => CIN,
SUM => SUM,
COUT => COUT );

32

DSD Lab Report

STIM_PROC: PROCESS
BEGIN
A<='0','1' AFTER 40 NS;
B<='0','1' AFTER 20 NS,'0' AFTER 40 NS,'1' AFTER 60 NS,'0' AFTER 80 NS;
CIN<='0','1' AFTER 10 NS,'0' AFTER 20 NS,'1' AFTER 30 NS,'0' AFTER 40 NS,'1' AFTER 50 NS,'0'
AFTER 60 NS,'1' AFTER 70 NS,'1' AFTER 80 NS;
WAIT;
END PROCESS;
END;

OUTPUT

RESULT
Implemented full adder in data flow model and verified the output.

33

DSD Lab Report

3.COMPARATOR (4 BIT)
AIM
To simulate a comparator in data flow model.

THEORY
A comparator circuit compares two numbers and if they are equal the output EQUAL is made to one and
GREATER and LESS set to 0.If the first number is greater than second number then GREATER is set to one and rest to
0.Similerly if first number is less than second number LESS is set to1.

SCEMATIC DIAGRAM

VHDL CODE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY COMPARATOR_4BIT IS
PORT ( A,B : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
EQUAL,LESS,GREATER : OUT STD_LOGIC);
END COMPARATOR_4BIT;
ARCHITECTURE DATAFLOW OF COMPARATOR_4BIT IS
BEGIN
EQUAL <= '1' WHEN A=B ELSE '0';

34

DSD Lab Report

LESS <= '1' WHEN A<B ELSE '0';
GREATER <= '1' WHEN A>B ELSE '0';
END DATAFLOW;

TEST BENCH
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TB_COMPARATOR_4BIT IS
END TB_COMPARATOR_4BIT;
ARCHITECTURE DATAFLOW OF TB_COMPARATOR_4BIT IS

COMPONENT COMPARATOR_4BIT
PORT(
A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
EQUAL : OUT STD_LOGIC;
LESS : OUT STD_LOGIC;
GREATER : OUT STD_LOGIC
);
END COMPONENT;

SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');

SIGNAL B : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL EQUAL : STD_LOGIC;
SIGNAL LESS : STD_LOGIC;
SIGNAL GREATER : STD_LOGIC;
BEGIN
UUT: COMPARATOR_4BIT PORT MAP (
A => A,
B => B,
EQUAL => EQUAL,
LESS => LESS,
GREATER => GREATER
);
STIM_PROC: PROCESS
BEGIN
A<="1000","0011" AFTER 20 NS,"0000" AFTER 30 NS;
B<="1000","0111" AFTER 10 NS,"0000" AFTER 30 NS;
WAIT;
END PROCESS;
END;

35

DSD Lab Report

OUTPUT

RESULT
Implemented 4 bit comparator in data flow model and verified the output.

36

DSD Lab Report

4. SHIFT REGISTER 16 BIT AND 64 BIT

AIM
To implement 16 bit and 64 bit shift registers in dataflow model

THEORY
A shift register shifts the bits after every clock pulse. They are mainly of 4 types SISO (Serial In Serial Out) ,
SIPO(Serial In Parallel Out), PISO(Parallel In Serial Out), PIPO(Parallel In Parallel Out).
In SISO there will be one bit input and one bit output the applied input will be available at the output after certain
number of clock cycle (size of register).

a)16 BIT SHIFT REGISTER (SISO)

SCHEMATIC DIAGRAM

VHDL CODE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SHIFT_REGISTER_SISO IS
PORT ( A, CLK : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END SHIFT_REGISTER_SISO;

37

DSD Lab Report

ARCHITECTURE DATAFLOW OF SHIFT_REGISTER_SISO IS

SIGNAL N : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
N <= A & N(15 DOWNTO 1) WHEN(CLK = '1' AND CLK'EVENT) ELSE
N;
Y<=N(0);
END DATAFLOW;

TEST BENCH
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TB_1 IS
END TB_1;
ARCHITECTURE DATAFLOW OF TB_1 IS
COMPONENT SHIFT_REGISTER_SISO
PORT(
A : IN STD_LOGIC;
Y : OUT STD_LOGIC;
CLK : IN STD_LOGIC
);
END COMPONENT;
SIGNAL A : STD_LOGIC := '0';
SIGNAL CLK : STD_LOGIC := '0';
SIGNAL Y : STD_LOGIC;
CONSTANT CLK_PERIOD : TIME := 10 NS;
BEGIN
UUT: SHIFT_REGISTER_SISO PORT MAP (
A => A,
Y => Y,
CLK => CLK
);
CLK_PROCESS :PROCESS
BEGIN
CLK <= '1';
WAIT FOR CLK_PERIOD/2;
CLK <= '0';
WAIT FOR CLK_PERIOD/2;
END PROCESS;

38

DSD Lab Report

STIM_PROC: PROCESS
BEGIN
A <= '1', '0' AFTER 50 NS,'1' AFTER 110 NS,'0' AFTER 140 NS;
WAIT;
END PROCESS;
END;

OUTPUT

B) 64 BIT SHIFT REGISTER

SCHEMATIC DIAGRAM

39

DSD Lab Report

VHDL CODE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SHIFT_REGISTER_SISO IS
PORT ( A,CLK : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END SHIFT_REGISTER_SISO;
ARCHITECTURE DATAFLOW OF SHIFT_REGISTER_SISO IS
SIGNAL N : STD_LOGIC_VECTOR(64 DOWNTO 0);
BEGIN
N <= A & N(64 DOWNTO 1) WHEN(CLK = '1' AND CLK'EVENT) ELSE
N;
Y<=N(0);
END DATAFLOW;

TEST BENCH
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TB_1 IS
END TB_1;
ARCHITECTURE DATAFLOW OF TB_1 IS
COMPONENT SHIFT_REGISTER_SISO
PORT(
A : IN STD_LOGIC;
Y : OUT STD_LOGIC;
CLK : IN STD_LOGIC
);
END COMPONENT;
SIGNAL A : STD_LOGIC := '0';
SIGNAL CLK : STD_LOGIC := '0';
SIGNAL Y : STD_LOGIC;
CONSTANT CLK_PERIOD : TIME := 10 NS;
BEGIN
UUT: SHIFT_REGISTER_SISO PORT MAP (
A => A,
Y => Y,
CLK => CLK
);

40

DSD Lab Report

CLK_PROCESS :PROCESS
BEGIN
CLK <= '1';
WAIT FOR CLK_PERIOD/2;
CLK <= '0';
WAIT FOR CLK_PERIOD/2;
END PROCESS;
STIM_PROC: PROCESS
BEGIN
A <= '1', '0' AFTER 70 NS,'1' AFTER 200 NS,'0' AFTER 210 NS,'1' AFTER 220 NS;
WAIT;
END PROCESS;
END;

OUTPUT

RESULT
Implemented 16 bit and 64 bit SISO shift register in data flow model and verified the result.

41

DSD Lab Report

5. MULTIPLEXER WITH TRISTATING

AIM
To simulate a multiplexer(4X1) in dataflow model.

THEORY
A mux selects one of the inputs and route to the output according to the select line values.The truth table below
describes its operation.

ENABLE
1
1
1
1
0

INPUT

SELECT LINE
S(1) S(0)

OUTPUT

00
01
10
11
XX

A(0)
A(1)
A(2)
A(3)
Z

A3-A0

SCHEMATIC DIAGRAM

VHDL CODE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX_TRISTATE IS
PORT ( A : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
S : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ENABLE : IN STD_LOGIC;
O : OUT STD_LOGIC);
END MUX_TRISTATE;
ARCHITECTURE DATAFLOW OF MUX_TRISTATE IS
BEGIN

42

DSD Lab Report

O <= A(0)WHEN (ENABLE ='1' AND S ="00") ELSE
A(1)WHEN (ENABLE ='1' AND S ="01") ELSE
A(2)WHEN (ENABLE ='1' AND S ="10") ELSE
A(3)WHEN (ENABLE ='1' AND S ="11") ELSE
'Z';
END DATAFLOW;

TEST BENCH
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TB_MUX IS
END TB_MUX;
ARCHITECTURE DATAFLOW OF TB_MUX IS
COMPONENT MUX_TRISTATE
PORT(
A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ENABLE : IN STD_LOGIC;
O : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL S : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL ENABLE : STD_LOGIC := '0';
SIGNAL O : STD_LOGIC;
BEGIN
UUT: MUX_TRISTATE PORT MAP (
A => A,
S => S,
ENABLE => ENABLE,
O => O
);
STIM_PROC: PROCESS
BEGIN
A<="0110","1100" AFTER 100 NS;
S<="00","01" AFTER 20 NS,"10" AFTER 40 NS,"11" AFTER 60 NS,"00" AFTER 100 NS,"01" AFTER 120
NS,"10" AFTER 140 NS,"11" AFTER 160 NS;
ENABLE <='1','0' AFTER 60 NS,'1' AFTER 100 NS;
WAIT;
END PROCESS;
END;

43

DSD Lab Report

OUTPUT

RESULT
Implemented 4X1 mux with tri-state in data flow model and varified the output.

44

DSD Lab Report

6. DECODER WITH TRISTATING(2:4 DECODER)

AIM
To design a 2X4 decoder in data flow model with High Impedance state

THEORY
A decoder decodes the input. Generally according to the input one of the output goes high and all
other outputs are zeros. The truth table below describes its operation.

ENABLE

OUTPUT

INPUT
A(1) A(0)
00

01

0010

10

0100

11

1000

XX

0001

SCHEMATIC DIAGRAM

VHDL CODE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DECODER2_4 IS
PORT ( A : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
ENABLE : IN STD_LOGIC;

45

DSD Lab Report

Y : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END DECODER2_4;
ARCHITECTURE DATAFLOW OF DECODER2_4 IS
BEGIN
Y<="0001" WHEN ENABLE='1' AND A="00" ELSE
"0010" WHEN ENABLE='1' AND A="01" ELSE
"0100" WHEN ENABLE='1' AND A="10" ELSE
"1000" WHEN ENABLE='1' AND A="11" ELSE
"ZZZZ";
END DATAFLOW;

TEST BENCH
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TB_DECODER_2_4 IS
END TB_DECODER_2_4;
ARCHITECTURE DATAFLOW OF TB_DECODER_2_4 IS
COMPONENT DECODER2_4
PORT(
A : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ENABLE : IN STD_LOGIC;
Y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
SIGNAL A : STD_LOGIC_VECTOR(1 DOWNTO 0) := (OTHERS => '0');
SIGNAL ENABLE : STD_LOGIC := '0';
SIGNAL Y : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
UUT: DECODER2_4 PORT MAP (
A => A,
ENABLE => ENABLE,
Y => Y
);
STIM_PROC: PROCESS
BEGIN
A<="00","11" AFTER 50 NS,"01" AFTER 70 NS,"10" AFTER 120 NS,"00" AFTER 155 NS;
ENABLE<='1','0' AFTER 20 NS,'1' AFTER 45 NS,'0' AFTER 100NS,'1' AFTER 130 NS;
WAIT;
END PROCESS;
END;

46

DSD Lab Report

OUTPUT

RESULT
Implemented 2X4 decoder with tri-state in data flow model and verified the output.

47

DSD Lab Report

MODULE III: BEHAVIORAL MODELING

48

DSD Lab Report

1.FOUR BIT BINARY COUNTER

AIM
To implement 4 bit binary adder in behavioral model.

THEORY
A 4 bit up counter counts from 0000 to 1111(total 16 states) .When the preset input is high then it sets all the
output bits high (1111) and when clear input is high it clears all the output bits (0000).

SCHEMATIC DIAGRAM

VHDL CODE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY FOUR_BIT_UP_COUNTER IS
PORT ( CLK,CLR,PR : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END FOUR_BIT_UP_COUNTER;
ARCHITECTURE BEHAVIORAL OF FOUR_BIT_UP_COUNTER IS
SIGNAL S:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";
BEGIN
Q<=S;
PROCESS(CLK)

49

DSD Lab Report

BEGIN
IF(CLK='1' AND CLK'EVENT) THEN
IF(CLR='1' AND PR='0') THEN S<="0000";
ELSIF(CLR='0' AND PR='1') THEN S<="1111";
ELSIF(CLR='0' AND PR='0') THEN
S<=S+"0001";
END IF;
END IF;
END PROCESS;
END BEHAVIORAL;

TEST BENCH
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TB_FOUR_BIT_UP_COUNTER IS
END TB_FOUR_BIT_UP_COUNTER;
ARCHITECTURE BEHAVIOR OF TB_FOUR_BIT_UP_COUNTER IS
COMPONENT FOUR_BIT_UP_COUNTER
PORT(
CLK : IN STD_LOGIC;
CLR : IN STD_LOGIC;
PR : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
SIGNAL CLK : STD_LOGIC := '0';
SIGNAL CLR : STD_LOGIC := '0';
SIGNAL PR : STD_LOGIC := '0';
SIGNAL Q : STD_LOGIC_VECTOR(3 DOWNTO 0);
CONSTANT CLK_PERIOD : TIME := 10 NS;
BEGIN
UUT: FOUR_BIT_UP_COUNTER PORT MAP (
CLK => CLK,
CLR => CLR,
PR => PR,
Q => Q
);
CLK_PROCESS :PROCESS
BEGIN
CLK <= '0';
WAIT FOR CLK_PERIOD/2;
CLK <= '1';
WAIT FOR CLK_PERIOD/2;
END PROCESS;

STIM_PROC: PROCESS
BEGIN

50

DSD Lab Report

CLR<='0','1' AFTER 95 NS,'0' AFTER 105 NS;
PR<='0','1' AFTER 140 NS,'0' AFTER 155 NS;
WAIT;
END PROCESS;
END;

OUTPUT

RESULT
Implemented 4 bit binary counter in behavioral model and verified the output.

51

DSD Lab Report

2. UP/DOWN DECADE COUNTER

AIM
To simulate a UP/DOWN decade in behavioral model.

THEORY
An up/down decade counter is a mod-10 counter which counts from 0 to 9 (up) or 9 to 0(down) on each clock
pulse.when mode input is high then it will work as a up counter and a down counter when mode is logic low.

SCHEMATIC DIAGRAM

VHDL CODE

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DECADE_COUNTER IS
PORT ( CLK,MODE: IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END DECADE_COUNTER;
ARCHITECTURE BEHAVIORAL OF DECADE_COUNTER IS
BEGIN
PROCESS(CLK)

52

DSD Lab Report

VARIABLE S:STD_LOGIC_VECTOR(3 DOWNTO 0):="1111";
VARIABLE W:STD_LOGIC_VECTOR(3 DOWNTO 0):="1010";
BEGIN
IF(CLK='1' AND CLK'EVENT) THEN
IF (MODE='1') THEN S:=S+'1';
IF(S="1010") THEN S:="0000";
END IF;
Q<=S;
ELSIF (MODE='0') THEN W:=W-'1';
IF(W="1111") THEN W:="1001";
END IF;
Q<=W;
ELSE

Q<="ZZZZ";

END IF;
END IF;
END PROCESS;
END BEHAVIORAL;

TEST BENCH
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY TB_DECADE IS
END TB_DECADE;
ARCHITECTURE BEHAVIOR OF TB_DECADE IS
COMPONENT DECADE_COUNTER
PORT(
CLK : IN STD_LOGIC;
MODE : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
SIGNAL CLK : STD_LOGIC := '0';
SIGNAL MODE : STD_LOGIC := '0';
SIGNAL Q : STD_LOGIC_VECTOR(3 DOWNTO 0);

53

DSD Lab Report

CONSTANT CLK_PERIOD : TIME := 5 NS;
BEGIN
UUT: DECADE_COUNTER PORT MAP (
CLK => CLK,
MODE => MODE,
Q => Q
);
CLK_PROCESS :PROCESS
BEGIN
CLK <= '0';
WAIT FOR CLK_PERIOD/2;
CLK <= '1';
WAIT FOR CLK_PERIOD/2;
END PROCESS;
STIM_PROC: PROCESS
BEGIN
MODE<='0','1' AFTER 70 NS;
WAIT;
END PROCESS;
END;

OUTPUT

RESULT
Implemented UP/DOWN decade counter in behavioral model and verified the output

54

DSD Lab Report

3. BCD ADDER AND SUBTRACTOR

AIM
To implement a BCD adder subtractor and in behavioural model.

THEORY
BCD adder is used to add two BCD numbers.The valid BCD numbers are from 0(0000) to
9(1001).The result should be converted to a valid format if it exceeds 9. Same for subtractor there is an
additional output borrow If borrow=1 then the result is a negative number If borrow=0 then the
result is a positive number .
a. BCD ADDER
SCHEMATIC

VHDL CODE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BCD_ADDER IS
PORT ( A,B : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
Y : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END BCD_ADDER;
ARCHITECTURE BEHAVIORAL OF BCD_ADDER IS
BEGIN
PROCESS(A,B)

55

DSD Lab Report

VARIABLE TEMP:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
TEMP := ("0000" & A) +("0000" & B);
IF(TEMP >"00001001") THEN
TEMP(3 DOWNTO 0):= TEMP(3 DOWNTO 0)-"1010";
TEMP(7 DOWNTO 4):="0001";
END IF;
Y<=TEMP;
END PROCESS;
END BEHAVIORAL;

TEST BENCH
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY TB_BCDADDER IS
END TB_BCDADDER;
ARCHITECTURE BEHAVIOR OF TB_BCDADDER IS
COMPONENT BCD_ADDER
PORT(
A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Y : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL B : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL Y : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
UUT: BCD_ADDER PORT MAP (
A => A,
B => B,
Y => Y
);
STIM_PROC: PROCESS
BEGIN
A<="0111","1001" AFTER 10 NS,"1000" AFTER 30 NS,"0010" AFTER 40 NS;
B<="0111","1001" AFTER 20 NS,"0001" AFTER 30 NS,"0000" AFTER 40 NS;
WAIT;
END PROCESS;
END;

56

DSD Lab Report

WAVE FORM

b. BCD SUBTRACTOR
SCHEMATIC DIAGRAM

If borrow=1 then the result is a

negative number

If borrow=0 then the result is a positive number

VHDL CODE:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY BCD_SUBTRACTOR IS
PORT ( A,B : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
Y : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
BORROW:OUT STD_LOGIC);

57

DSD Lab Report

END BCD_SUBTRACTOR ;
ARCHITECTURE BEHAVIORAL OF BCD_SUBTRACTOR IS
BEGIN
PROCESS(A,B)
VARIABLE TEMP:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF (A>=B) THEN
TEMP := A-B;
BORROW<='0';
ELSIF(B>A) THEN
TEMP := B-A;
BORROW<='1';
END IF;
Y<=TEMP;
END PROCESS;
END BEHAVIORAL;

TEST BENCH:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TB_BCD IS
END TB_BCD;
ARCHITECTURE BEHAVIOR OF TB_BCD IS
COMPONENT BCD_SUBTRACTOR
PORT(
A : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Y : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
BORROW : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL A : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL B : STD_LOGIC_VECTOR(3 DOWNTO 0) := (OTHERS => '0');
SIGNAL Y : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL BORROW : STD_LOGIC;

BEGIN
UUT: BCD_SUBTRACTOR PORT MAP (
A => A,
B => B,
Y => Y,
BORROW => BORROW
);
STIM_PROC: PROCESS
BEGIN
A<="0001","1000" AFTER 10 NS,"0000" AFTER 40 NS;
B<="0011","1000" AFTER 20 NS,"1001" AFTER 30 NS,"0000" AFTER 40 NS;

58

DSD Lab Report

WAIT;
END PROCESS;
END;

WAVE FORM

RESULT
Implemented BCD adder and subtractor in behavioral model and verified the output

59

DSD Lab Report

4 D-FLIP FLOP
AIM
To implement a D- FLIPFLOP in behavioural model.

THEORY
A D flip flop is one in which the output follows the input.If the clear signal is high the output goes low
irrespective of the input and also if the preset is high output goes to logic high.

TRUTH TABLE
CLR

PR

SCHEMATIC DIAGRAM

VHDL CODE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY D_FF IS
PORT ( D,CLK,PR,CLR : IN STD_LOGIC;
Q ,QBAR: OUT STD_LOGIC);
END D_FF;

60

DSD Lab Report

ARCHITECTURE BEHAVIORAL OF D_FF IS

SIGNAL S: STD_LOGIC :='0';
BEGIN
Q<=S;
QBAR<=NOT S;
PROCESS(CLK,CLR,PR)
BEGIN
IF(CLR='1' AND PR='0') THEN
S<='0';
ELSIF(CLR='0' AND PR='1') THEN
S<='1';
ELSIF (PR='1' AND CLR='1') THEN
S<='X';
ELSIF(CLR='0' AND PR='0') THEN
IF (RISING_EDGE(CLK)) THEN
IF(D='0') THEN
S<='0';
ELSIF(D='1') THEN S<='1';
END IF;
END IF;
END IF;
END PROCESS;
END BEHAVIORAL;

TEST BENCH
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY TB_D_FF IS
END TB_D_FF;
ARCHITECTURE BEHAVIOR OF TB_D_FF IS
-- COMPONENT DECLARATION FOR THE UNIT UNDER TEST (UUT)
COMPONENT D_FF
PORT(
D : IN STD_LOGIC;
CLK : IN STD_LOGIC;
PR : IN STD_LOGIC;
CLR : IN STD_LOGIC;
Q : OUT STD_LOGIC;
QBAR : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL D : STD_LOGIC := '0';
SIGNAL CLK : STD_LOGIC := '0';
SIGNAL PR : STD_LOGIC := '0';
SIGNAL CLR : STD_LOGIC := '0';
SIGNAL Q : STD_LOGIC;
SIGNAL QBAR : STD_LOGIC;

61

DSD Lab Report

-- CLOCK PERIOD DEFINITIONS
CONSTANT CLK_PERIOD : TIME := 10 NS;
BEGIN
-- INSTANTIATE THE UNIT UNDER TEST (UUT)
UUT: D_FF PORT MAP (
D => D,
CLK => CLK,
PR => PR,
CLR => CLR,
Q => Q,
QBAR => QBAR
);
-- CLOCK PROCESS DEFINITIONS
CLK_PROCESS :PROCESS
BEGIN
CLK <= '0';
WAIT FOR CLK_PERIOD/2;
CLK <= '1';
WAIT FOR CLK_PERIOD/2;
END PROCESS;

-- STIMULUS PROCESS
STIM_PROC: PROCESS
BEGIN
D<='0','1' AFTER 35 NS,'0' AFTER 70 NS,'1' AFTER 80 NS;
PR<='1','0' AFTER 20 NS,'1' AFTER 85 NS;
CLR<='0','1' AFTER 40 NS,'0' AFTER 50 NS;
WAIT;
END PROCESS;
END;

OUTPUT

RESULT
Implemented D flip flop in behavioural model and variefied the result.

62

DSD Lab Report

5 T-FLIP FLOP
AIM
To implement a T- FLIPFLOP in behavioural model.

THEORY
A T flip flop is one in which the output toggles if input is logic 1.output remains the same if
input is logic 0.
TRUTH TABLE
T

Qn

Qn+1

SCHEMATIC DIAGRAM

VHDL CODE
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY T_FF IS
PORT ( T,CLK,PR,CLR : IN STD_LOGIC;
Q : OUT STD_LOGIC;
QBAR: OUT STD_LOGIC );
END T_FF;

63

DSD Lab Report

ARCHITECTURE BEHAVIORAL OF T_FF IS

SIGNAL S: STD_LOGIC:='0';
BEGIN
Q<=S;
QBAR<= NOT S;
PROCESS(CLK)
BEGIN
IF RISING_EDGE(CLK) THEN
IF(PR='1' AND CLR='0') THEN S<='1';
ELSIF(PR='0' AND CLR='1') THEN S<='0';
ELSIF(PR='0' AND CLR='0') THEN
IF(T='1') THEN
S<=NOT S;
ELSE S<=S;
END IF;
ELSE S<='X';
END IF;
END IF;
END PROCESS;
END BEHAVIORAL;

TEST BENCH
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TB_TFF IS
END TB_TFF;
ARCHITECTURE BEHAVIOR OF TB_TFF IS

COMPONENT T_FF
PORT(
T : IN STD_LOGIC;
CLK : IN STD_LOGIC;
PR : IN STD_LOGIC;
CLR : IN STD_LOGIC;
Q : OUT STD_LOGIC;
QBAR : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL T : STD_LOGIC := '0';
SIGNAL CLK : STD_LOGIC := '0';
SIGNAL PR : STD_LOGIC := '0';
SIGNAL CLR : STD_LOGIC := '0';
SIGNAL Q : STD_LOGIC;
SIGNAL QBAR : STD_LOGIC;
CONSTANT CLK_PERIOD : TIME := 10 NS;

64

DSD Lab Report

BEGIN
UUT: T_FF PORT MAP ( T => T,
CLK => CLK,
PR => PR,
CLR => CLR,
Q => Q,
QBAR => QBAR
);
CLK_PROCESS :PROCESS
BEGIN
CLK <= '0';
WAIT FOR CLK_PERIOD/2;
CLK <= '1';
WAIT FOR CLK_PERIOD/2;
END PROCESS;
STIM_PROC: PROCESS
BEGIN
T<='0','1' AFTER 35 NS,'0' AFTER 70 NS,'1' AFTER 80 NS;
PR<='1','0' AFTER 20 NS,'1' AFTER 85 NS;
CLR<='0','1' AFTER 40 NS,'0' AFTER 50 NS;
WAIT;
END PROCESS;
END;

OUTPUT

RESULT
Implemented T flip flop in behavioural model and verified the output.

65

DSD Lab Report

6 . JK FLIP FLOP
AIM
To implement a JK- FLIPFLOP in behavioural model.

THEORY
The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the S = R = 1
condition as a "flip" or toggle command.The characteristic equation of the JK flip-flop is

TRUTH TABLE
J
0

K
0

Qn+1
Qn

SCHEMATIC DIAGRAM

66

DSD Lab Report

VHDL CODE
ENTITY JK_FF IS
PORT ( J,K,CLK,CLR,PR : IN STD_LOGIC;
Q,QBAR : OUT STD_LOGIC);
END JK_FF;

ARCHITECTURE BEHAVIORAL OF JK_FF IS

SIGNAL S:STD_LOGIC:='0';
SIGNAL A:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
Q<= S;
QBAR<= NOT S;
A<=J&K;
PROCESS(CLK)
BEGIN
IF(CLK='1' AND CLK'EVENT) THEN
IF(CLR='1' AND PR='0') THEN S<='0';
ELSIF(CLR='0' AND PR='1') THEN S<='1';
ELSIF(CLR='0' AND PR='0') THEN
CASE A IS
WHEN "00" => S<=S;
WHEN "01" => S<='0';
WHEN "10" => S<='1';
WHEN "11" => S<=NOT S;
WHEN OTHERS => NULL;
END CASE;
END IF;
END IF;
END PROCESS;
END BEHAVIORAL;

67

DSD Lab Report

TEST BENCH:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY TB_JK_FF IS
END TB_JK_FF;
ARCHITECTURE BEHAVIOR OF TB_JK_FF IS
COMPONENT JK_FF
PORT(
J : IN STD_LOGIC;
K : IN STD_LOGIC;
CLK : IN STD_LOGIC;
CLR : IN STD_LOGIC;
PR : IN STD_LOGIC;
Q : OUT STD_LOGIC;
QBAR : OUT STD_LOGIC
);
END COMPONENT;
SIGNAL J : STD_LOGIC := '0';
SIGNAL K : STD_LOGIC := '0';
SIGNAL CLK : STD_LOGIC := '0';
SIGNAL CLR : STD_LOGIC := '0';
SIGNAL PR : STD_LOGIC := '0';

SIGNAL Q : STD_LOGIC;
SIGNAL QBAR : STD_LOGIC;

CONSTANT CLK_PERIOD : TIME := 10 NS;

BEGIN
UUT: JK_FF PORT MAP (
J => J,
K => K,
CLK => CLK,
CLR => CLR,
PR => PR,
Q => Q,
QBAR => QBAR
);

CLK_PROCESS :PROCESS
BEGIN
CLK <= '0';

68

DSD Lab Report

WAIT FOR CLK_PERIOD/2;
CLK <= '1';
WAIT FOR CLK_PERIOD/2;
END PROCESS;
STIM_PROC: PROCESS
BEGIN
J<='0','1' AFTER 35 NS,'0' AFTER 60 NS,'1' AFTER 70 NS;
K<='0','1' AFTER 15 NS,'0' AFTER 45 NS,'1' AFTER 60 NS;
PR<='1','0' AFTER 20 NS,'1' AFTER 95 NS;
CLR<='0','1' AFTER 70 NS,'0' AFTER 80 NS;
WAIT;
END PROCESS;
END;

OUTPUT

RESULT
Implemented JK flip flop in behavioural model and verified the output.

69