Full Adder Test Bench and VHDL Code
Full Adder Test Bench and VHDL Code
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full_Adder code for rtl simulation
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entity full_adder is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
cout : out STD_LOGIC;
sum : out STD_LOGIC);
end full_adder;
architecture Behavioral of full_adder is
begin
sum <= a xor b xor cin;
cout <= ( a and b) or (b and cin) or (cin and a);
end Behavioral;
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test bench code for full adder
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-- Stimulus process
stim_proc: process
begin
wait for 100 ns;
a <= '0';
b <= '0';
cin <= '0';
wait for 100 ns;
a <= '0';
b <= '0';
cin <= '1';
wait for 100 ns;
a <= '0';
b <= '1';
cin <= '0';
wait for 100 ns;
a <= '0';
b <= '1';
cin <= '1';
wait for 100 ns;
a <= '1';
b <= '0';
cin <= '0';
wait for 100 ns;
a <= '1';
b <= '0';
cin <= '1';
wait for 100 ns;
a <= '1';
b <= '1';
cin <= '0';
wait for 100 ns;
a <= '1';
b <= '1';
cin <= '1';
wait for 100 ns;
wait;
end process;