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Vidyarthiplus Question Papers: Anna University, Chennai

This document is a question paper for an electronics and communication engineering exam on VLSI design. It contains 15 questions testing students' knowledge on topics like technology-CAD issues, lambda layout rules, device modeling, CMOS circuit power losses, synchronizers, CMOS testing types, logic verification, structural vs switch level modeling, gate primitives, I-V characteristics of MOS devices, scaling and reliability concepts, transistor sizing, delay estimation, pipelining, reducing switching activity, design for testability concepts, silicon debug principles, boundary scan techniques, and designing priority encoders and multiplexers using HDL. Students are required to answer all questions which are worth a total of 100 marks.

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111 views3 pages

Vidyarthiplus Question Papers: Anna University, Chennai

This document is a question paper for an electronics and communication engineering exam on VLSI design. It contains 15 questions testing students' knowledge on topics like technology-CAD issues, lambda layout rules, device modeling, CMOS circuit power losses, synchronizers, CMOS testing types, logic verification, structural vs switch level modeling, gate primitives, I-V characteristics of MOS devices, scaling and reliability concepts, transistor sizing, delay estimation, pipelining, reducing switching activity, design for testability concepts, silicon debug principles, boundary scan techniques, and designing priority encoders and multiplexers using HDL. Students are required to answer all questions which are worth a total of 100 marks.

Uploaded by

srgperumal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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www.Vidyarthiplus.

com

Anna University , Chennai


Vidyarthiplus Question Papers
Reg. No. :

Question Paper Code : 21373


B.E./B.Tech DEGREE EXAMINATION , MAY/JUNE 2013
Sixth Semester
Electronics and Communication Engineering
EC 2354/EC 64 VLSI DESIGN
(Regulation 2008)
(Common to PTEC 2354 VLSI Design for B.E. (PartTime) fifth Semester Electronics and communication
Engineering Regulation 2009)
Time : Three hours

Maximum : 100 marks

Answer ALL questions.


PART A (10 X 2 = 20 marks)
1. List the various issues in Technology-CAD.

2. Define the lambda layout rules.

3. What is meant by design margin?

4. How do you define the term device modeling?

5. List the various power losses in CMOS circuits.

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www.Vidyarthiplus.com

6. Enumerate the features of synchronizers.

7. List the basic types of CMOS testing.

8. What is meant by logic verification?

9. Give the Comparison between structural and switch level


modelling.

10. What are gate primitives?

PART B (5 x 16 = 80 marks)
11. (a) Explain in detail about the ideal I-V characteristics and
non ideal I-V characteristics of a NMOS and PMOS devices.

(Or)

(b) (i) Explain in detail about the body effect and its effect
in NMOS and PMOS devices.
(8)

(ii) Derive the expression for DC transfer characteristics


of CMOS Inverter.
(8)

12. (a) (i) Explain in detail about the scaling concept and
reliability concept.

(8)

(ii) Describe in detail about the transistor sizing for the


performance in combinational networks.
(8)

(Or)

(b) Discuss in detail about the resistive and capacitive


delay estimation of a CMOS inverter circuit.

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www.Vidyarthiplus.com

13. (a) Explain in detail about the pipelining concept used in


sequential circuits.

(Or)

(b) Discuss the techniques to reduce switching activity in a


static and dynamic CMOS circuits.

14. (a) Explain the design for testability (DFT) concepts.

(Or)

(b) Explain the following terms,

(i) Silicon debug principles. (8)

(ii) Boundary scan techniques. (8)

15. (a) Design and develop the HDL project to realize the
function of a priority encoder using structural model.

(Or)

(b) (i) Write a data-flow model verilog HDL program for


the two input comparator circuit.
(8)

(ii) Write a behavioral level verilog HDL program for


the 1x8 Multiplexer circuit.

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