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Experiment 5: Aim: Eda Tool Used: Methodology

This document describes an experiment to design a 4:1 multiplexer at different levels of abstraction using an FPGA tool. It includes the methodology, truth table, logic expression, block diagram, Verilog code at gate, dataflow and behavioral levels, RTL schematic views, and output waveform for a 4:1 multiplexer. The aim was to implement the multiplexer using different modeling approaches and verify its operation through simulation. The results showed the multiplexer was successfully designed and simulated at various levels of abstraction.

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Thomas James
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22 views4 pages

Experiment 5: Aim: Eda Tool Used: Methodology

This document describes an experiment to design a 4:1 multiplexer at different levels of abstraction using an FPGA tool. It includes the methodology, truth table, logic expression, block diagram, Verilog code at gate, dataflow and behavioral levels, RTL schematic views, and output waveform for a 4:1 multiplexer. The aim was to implement the multiplexer using different modeling approaches and verify its operation through simulation. The results showed the multiplexer was successfully designed and simulated at various levels of abstraction.

Uploaded by

Thomas James
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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FPGA/ CPLD LAB

EXPERIMENT 5
AIM : To design a 4:1 multiplexer at different levels of modelling.
EDA TOOL USED : Xilinx ISE 8.1i
METHODOLOGY : A digital multiplexer is a combinational circuit that selects one digital
information from several sources and transmits the selected information on a single output line. A
mux is also called a data selector since it selects one of many inputs. If the number of n input lines is
equal to 2m then m select lines are required to select one of the input lines, for example, if there are 4
inputs, then 2 select lines are required.
Truth Table :
Select lines

Output

S1

S0

(Y)

I0

I1

I2

I3

Expression : Y = S1 S0 I0 + S1 S0 I1 + S1 S0 I2 + S1 S0 I3
Block Diagam :

Fig 5.1 Block diagram of 4 : 1 MUX

VERILOG CODE :
Gate level Modelling
module muxb(I0, I1, I2, I3, S0, S1, Y);
input I0,I1,I2,I3,S0,S1;

output Y;

wire t0,t1,r0,r1,r2,r3;

not(t0,S0); not(t1,S1); and(r0,I0,t0,t1); and(r1,I1,S0,t1);


and(r2,I2,t0,S1); and(r3,I3,S0,S1);

or(Y,r0,r1,r2,r3);

endmodule
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FPGA/ CPLD LAB

Data flow level Modelling


Using Continuous statements:
module muxd1(I0, I1, I2, I3, S0, S1, Y);
input I0,I1,I2,I3,S0,S1;

output Y;

assign {Y}=(I0&(~S1)&(~S0))|(I1&(~S1)&(S0))|(I2&(S1)&(~S0))|(I3&(S1)&(S0));
endmodule
Using conditional statement:
module muxd2(I0, I1, I2, I3, S0, S1, Y);
input I0,I1,I2, I3,S0,S1;

output Y;

assign {Y}=S0?(S1?I3:I1):(S1?I2:I0);

endmodule
Behavioural level Modelling
module muxb(I,S,Y);
input [3:0]I; input [1:0]S; output reg Y;
always@(I,S)
begin
case(S)
0: begin

Y=I[0]; end

1: begin

Y=I[1]; end

2: begin

Y=I[2]; end

3: begin

Y=I[3]; end

endcase

end

endmodule

RTL SCHEMATIC VIEW :


Gate level Modelling

Fig 5.2 RTL schematic of 4 : 1 MUX


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FPGA/ CPLD LAB

Data flow level Modelling

(a)

(b)
Fig 5.3 (a) & (b) RTL schematic of 4 : 1 MUX

Behavioural level Modelling

(a)

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FPGA/ CPLD LAB

(b)
Fig 5.4 (a) & (b) RTL schematic of 4 : 1 MUX

OUTPUT WAVEFORM :

Fig 5.5 Output waveform of 4 : 1 MUX

RESULT : Successfully implemented 4 : 1 MUX using different levels of modelling and verified
its operation through simulation.

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