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Assignment VLSI Technology Last Date of Submission: 18/10/2011

This document outlines 22 assignments related to VLSI technology that are due on October 18, 2011. The assignments include explaining noise margin and deriving expressions for voltage transfer characteristics for inverters with resistive and CMOS loads. Other assignments involve solving examples, explaining CMOS ring oscillators and power calculations, drawing various digital circuits using transmission gates and CMOS implementations, and designing logic gates using pass transistor and domino CMOS logic. Additional assignments cover topics like voltage bootstrapping, latchup, charge sharing, TSPC logic, dynamic logic, DRAM and SRAM cells.

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17 views2 pages

Assignment VLSI Technology Last Date of Submission: 18/10/2011

This document outlines 22 assignments related to VLSI technology that are due on October 18, 2011. The assignments include explaining noise margin and deriving expressions for voltage transfer characteristics for inverters with resistive and CMOS loads. Other assignments involve solving examples, explaining CMOS ring oscillators and power calculations, drawing various digital circuits using transmission gates and CMOS implementations, and designing logic gates using pass transistor and domino CMOS logic. Additional assignments cover topics like voltage bootstrapping, latchup, charge sharing, TSPC logic, dynamic logic, DRAM and SRAM cells.

Uploaded by

harsh_shukla131313
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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Assignment VLSI Technology

Last Date of submission : 18/10/2011

Explain noise margin for inverter.

2
3

Define VIL and VIH and derive expression for all VTC points for resistive load
inverter.
Explain CMOS inverter and derive expression for all VTC points for it.

Solved examples-5.1,5.2

Explain CMOS ring oscillator.

Explain dynamic capacitive power and dynamic short circuit power for CMOS
inverter

Draw the following digital circuit using transmission gate


1. 2:1 MUX
2. 4:1 MUX
3. 2 input ex-or gate
4. F=AB+AC+ABC
8 Draw the following CMOS based circuit :
1. CMOS SR latch based on NOR2
2. CMOS SR latch based on NAND2
3. CLOCKED NOR based SR latch
4. CMOS AOI realization of the JK latch
5. CMOS implementation of the D-Latch
6. CMOS negative edge-triggered master slave D FF
9 Draw the following digital circuit using Complementary Pass transistor logic
1. 2 input AND and NAND Gate
2. 2input OR and NOR Gate
3. 2 input Ex-OR and Ex-NOR Gate
4. 1 bit Full adder
10 Design 4 input NAND Gate using pass transistor
11 What is DOMINO logic? Explain in detail.
12 Write short notes on 1. Voltage bootstrapping
2. Latch up
13 Implement (A+B)C using cascade domino CMOS logic
14 Implement AB+(C+D)(E+F)+GH using domino CMOS logic
15 Draw 4 stage carry look ahead adder using multiple output domino CMOS gate
16 Using NORA implement the function AB+(C+D)+(EF+G)
17 Draw the circuit diagram of a TSPC based rising edge-triggered DFF
18 Using TSPC implement the function AB+CD
19 Using dynamic logic implement the function (A(B+C)+DE)
20 Explain the concept of charge sharing and explain the method of how to remove it.
21 Write a short note on TSPC using pipelined dynamic CMOS.
22 Draw circuit diagram of 3T DRAM cell with its working and related voltage
waveforms.
23 Explain working principle of CMOS SRAM cell with necessary circuit diagram and
waveforms for read and write operation.

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