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Lab 1 Introduction To Verilog: Pinaki Ranjan Sarkar (SC13B110)

The document is a lab report submitted by Pinaki Ranjan Sarkar describing Verilog code implementations for basic logic gates, a full adder, full subtractor, and a converter from Gray code to binary code. It includes the Verilog code for each circuit, along with truth tables showing the expected input-output relationships. The observations section describes the truth tables for the logic gates, full adder, and full subtractor, as well as the Gray code to binary conversion table.

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41 views7 pages

Lab 1 Introduction To Verilog: Pinaki Ranjan Sarkar (SC13B110)

The document is a lab report submitted by Pinaki Ranjan Sarkar describing Verilog code implementations for basic logic gates, a full adder, full subtractor, and a converter from Gray code to binary code. It includes the Verilog code for each circuit, along with truth tables showing the expected input-output relationships. The observations section describes the truth tables for the logic gates, full adder, and full subtractor, as well as the Gray code to binary conversion table.

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PinakiRanjanSarkar
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© © All Rights Reserved
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Lab 1

Introduction to Verilog
Pinaki Ranjan Sarkar
(SC13B110)
Sub: VLSI Design
Date of Submission: February 4, 2015

Department: B Tech (Avionics)

Question 1:
Write a Verilog code for the basic gates and the universal gates and check the output.

Verilog Code:
module allgate(c,d,e,f,g,h,i,j,k,a,b);
input a,b;
output c,d,e,f,g,h;
assign c =a & b;
assign d =a | b;
assign e = ~a;
assign f= ~b;
assign g = a  b;
assign h = a  b;
assign i = ~(a & b);
assign k = ~(a | b);
endmodule

Output

Output of the all Gates

Question 2:
Write a Verilog code for Full adder and check the output.

Verilog Code:
module adder(s,c,a,b,d);
input a,b,d;
output s,c;
assign s = a  b  d;
assign c = a  b&dSa&b;
endmodule

Output

Full Adder outputs

Question 3:
Write a Verilog code for Full Subtractor and check the output.

Verilog Code:
module subtractor (s,c,a,b,d);
input a,b,d;
output s,c;
assign s = a  b  d;
assign c = a&a  dSb&d;
endmodule

Output

Full Subtractor outputs

Question 4:
Write a Verilog code for converting Gray code to Binary and check the output.

Verilog Code:
module gtob(y,a);
input [0:3]a;
output [0:3]y;
assign y[0] = a[0];
assign y[1] = a 1  y 0;
assign y[2] = a 2  y 1;
assign y[3] = a 3  y 2;
endmodule;

Output

Gray to Binary conversion

Observations:
For the Gates, The truth table of the gates:
Table 1: Truth table of OR-Gate
a b Y
0 0
0
0 1
1
1 0
1
1 0
1

Table 2: Truth
a
0
0
1
1

table of AND-Gate
b Y
0
0
1
0
0
0
0
1

Table 3: Truth table of NOT-Gate


a Y
0
1
1
0

Table 4: Truth
a
0
0
1
1

table of XOR-Gate
b Y
0
0
1
1
0
1
0
0

Table 5: Truth
a
0
0
1
1

table
b
0
1
0
0

of XNOR-Gate
Y
1
0
0
1

Observations:
The truth table of the Half Adder and Full Subtractor. And the Gray code to Binary conversion table.
Table 6: Truth
x y
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1

table of
z
C
0
0
1
0
0
0
1
1
0
0
1
1
0
1
1
1

Full Adder
S
0
1
1
0
1
0
0
1

Table 7: Truth table of Full Subtractor


x y z
D B
0 0 0
0 0
0 0 1
1 1
0 1 0
1 1
0 1 1
0 1
1 0 0
1 0
1 0 1
0 0
1 1 0
0 0
1 1 1
1 1

Table 8: Gray Code


Gray Code Decimal Equivalent
0000
0
0001
1
0011
2
0010
3
0110
4
0111
5
0101
6
0100
7
1100
8
1101
9
1111
10
1110
11
1010
12
1011
13
1001
14
1000
15

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