Xilinx 7 Series FPGA Libraries Guide for HDL Designs UG768 (v 13.4) January 18, 2012 © XILINX.& XILINX. %ilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for usein the development of designs to operate with Xilirxc hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means induding but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior mitten consent of Xilinx, Xilinx exprestly disclaims any liability arising out of your use of the Documentation. Yilinx reserves the night, atits sole discretion, to change the Documentation without notice at any time Xilinx ‘assumes no obligation to correct any errors contained in theDocumentation, orto advise you of any corrections or updates. Xilinx expressly disclaims any liability mi connection with technical support or assistance that may be provided to you in connection with the Information. ‘THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING ‘THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION. © Copyright 2002-2012 Xilinx Inc. All Rights Reserved. XILINX, the Xilinx logo, the Brand Window and other designated brands induded herein are trademarks of Xilinx, Inc. All other trademarks are the property of ther respective owners, Xilinx 7 Series FPGA Libraries Guide for HDL Designs 2 wwwxilinx.com UG768 (v 13.4) January 18, 2012© XILINX. Chapter 1 Introduction ‘This HDL guideis pat of the ISE® documentation collection. A separate version of this guideis available if you prefer to work with schematics ‘This guide contains the following: ‘Introduction. ‘+ Allist of design elements supported in this architecture, organized by functional categories. ‘+ Descriptions of each available primitive Design Entry Methods For each design clement in this guide, Xilinx evaluates four options for using the design. clement, and recommends what we believe is the best solution for you. The four options ‘+ Instantiation - This component can be instantiated directly into the design. This method is useful if you want to control the exact placement of theindividual blocks, ‘+ Inference - This component can be inferred by most supported synthesis tools. You should use this method if you want to have complete fleability and portability of the code to multiple architectures. Inference also gives the tools the ability to optimize for performance, area or power, as specified by the user to the synthesis tool + Coregen & Wizards - This component can be used through CORE Generator or other Wizards. You should use this method if you want to build large blocks of any FPGA primitive that cannot beinfarred. When using this flow, you will have to regenerate your cores for each architecture that you are targeting, ‘+ Macro Support - This component has a UniMacro that can be used. These components arein the UnilMacro library in the Alin tool, and are used to instantiate primitives that are too complex to instantiate by just using the primitives. The synthesis tools will automatically expand UniMacros to their underlying primitives. Xilinx 7 Series FPGA Libr UG768 (v 13.4) January 18, 2012 www. +8 Guide for HDL Designs inx.com 3Xilinx 7 Series FPGA Libraries Guide for HDL Designs wwwxilinx.com UG768 (v 13.4) January 18, 2012£ XILINX. Chapter 2 About Unimacros ‘This section describes the unimacros that can be used with this architecture The unimacros are organized alphabetically. ‘The following information is provided for each unimacro, where applicable + Name of element + Brief deserption + Schematic symbol + Logic table (if any) + Port deseiptions + Design Entry Method + Available attributes + Example instantiation code + Formore information Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012Chapter 2: About Unimacros £ XILINX: BRAM_SDP_MACRO Macro: Simple Dual Port RAM ‘were wor Introduction 7 series FPGA devices contain several block RAM memories that can be configured as general-purpose 36Kb or 18Kb RAM/ROM memories. These block RAM memories offer fast and fleable storage of large amounts of on-chip data Both read and write operations are fully synchronous to the supplied clock s) of the component. However, READ and WRITE ports can operate fully independently and asynchronously to each other, accessing, the same memory aay. Byte-enable write operations are possible, and an optional output register can be used to reduce the clock-to-out times of the RAM. Note This clement must be configured so that read and write ports have the same width. Port Description ‘Name Direction | Width (Bits) Function DO ‘Output _| See Configuration Table Data output bus addressed by RDADDR DI Taput See Configuration Table Data input bus addrerced by WRADDR ‘WRADDR, Tnpat ‘See Configuration Table ‘Waite/Read address input buses RDADDR WE Taput See Configuration Table Byte Wide Wite enable WREN, Input 1 Wite/Read enable RDEN om Taput 1 Output registers synchronous reret REGCE Tapa 1 (Output register dock enable input (valid only when DO-REGI) Xilinx 7 Series FPGA Libraries Guide for HDL Designs 6 wwwxilinx.com UG768 (v 13.4) January 18, 2012£ XILINX: Chapter 2: About Unimacros ‘Name Direction | Width (Bits) Function WRCLK, Tapat T ‘Waite/Read dock input RDCLK Port Configuration ‘This unimacro is aparameterizable version of the primitive, and can be instantiated only. Use this table to correctly configure the unimacro to meet design needs. DATA_WIDTH BRAM_SIZE ‘ADDR WE Ra 36K 9 8 36-19 36K 10 4 18K 9 18-10 eK 1 2 18K 10 9-5 eK 2 1 18K um 3 eK 8 1 18K 2 2 eK M4 1 18K 18 1 eK 15 1 18K u Design Entry Method ‘This unimacro is aparameterizable version of the primitive, and can be instantiated only. Consult the Port Configuration section to correctly configure this element to meet your design needs. Tneantiation Yer Tnference Ne CORE Generator and wicards Ne Maco support Recommended Available Attributes Attribute Type Allowed Values _| Default Description BRAM SZE String SOKb", "16K "18Kb ‘Configures RAMaz "S6Kb" or "IEK6' memory, DEVICE String ‘7SERIES| ‘7SERIES “Target hardware ardutecture DO_REG Integer On 0 ‘Avalue of | enables to the output registers totheRAM enabling quicker dodeto-out from the RAM at the expense of an added dock cycle of read latency Acvalue of O allows a read m one dock cycle but will have slower dock to out tuning. Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www xilinx.com 7Chapter 2: About Unimacros £ XILINX: Attribute Type Allowed Values Default Description INT Hexadeamal “Any 72 Bit Value ‘Allzeros Species the intial value on the output after configuration. READ_WIDTH, ‘WRITE_WIDTH Integer 36 Species the size of the DI and DO bases ‘The following combinations are allowed: © READ_WIDTH = ‘WRITE_WIDTH ©) Wasymmetric READ_WIDTH and WRITE_WIDTH must bein ‘the ratio of 2 or must be valuer allowed by the unisim (1,2, 4.8, 9,16, 18, 32, 36, 64,72) INIT_FILE String ‘ring representing Sle name and location, NONE ‘Name of the fle containing initial values ‘SIM_COLLISION_ CHECK String "ALL WARNING ONLY’ ‘GENERATE X_ ONLY’ ‘NONE ‘Allows modification ofthe amulation dehaviorifa memory collision oscars ‘The output is affected as flloves: © CALL". Waming produced and affected outputs/memory location go unkatowen (%). © WARNING_ONLY"- Waring produced and affected ‘cutputs/memery retain last value © "GENERATE_X_ONLY"- No warming. However, affected cutputsimemery go unknown 06) © NONE". No warming and affected outputs/memary retain last value, Note, Setting this toa value other than "ALL" can allow problems in the design go unnoticed during simulation, Care should be taken when changing the value of thir attubute. Please see the Synthesis ‘aid Sinulation Desig Guice for more ‘information SRVAL Hexadeamal “Any 72 Bit Value ‘Allzeroes Species the output value of on the DO port upon the assertion of the synchronous reset (RST) agnal INIT00t0 INTIF Hexadeamal “Any 256-Bit Value ‘Allzeroes ‘Allows specification of the sutial ‘contents of the 16Kb or 32K data memory array INITP_00t0 INITPLOF Hexadeamal “Any 256-Bit Value ‘Allzeroes ‘Allows specification of the intial contents of the 2Kb or 4b party data memory array Xilinx 7 Series FPGA Libraries Guide for HDL Designs UG768 (v 13.4) January 18, 2012© XILINX. Chapter 2: About Unimacros VHDL Instantiation Template Unless they already east, copy the following two statements and paste them before the entity declaration. t Sl valid values ace 1-72 (27-72 only valid when ARAM St2E—"36KD") x"000000000000e000000000000000000000000000000000000000000000000000") port aap ( Ana => ADDR, —- Input address, width defined by read/write pore depth Xilinx 7 Series FPGA Libraries Guide for HDL Designs UG76S (v 13.4) January 18, 2012 wewwaxllinx.com atChapter 2: About Unimacros € XILINX. bs Verilog Instantiation Template 11 spas srucie pincRO: Single Port RAM a 7 Series 1) siting uot tibraries Guide, version 13.4 ALIELLLLLLLALLELEU LUA ELELLT LETT UTLT LATTA ELLA TLE 1) exo weDeH | BRAMLETEE. | READ Depth | ADDR wide “ 1) watever | wRITE Depth | we width 1 a Ie 1 ers ‘Some | siz | Sb eae 19-36 ssom" | 1024 | ad-bie eee 19-36 nism" | 512, | Subse eee “10-18 ssom" | 20de | ar-bie pee 10-18 nism" | 1024 | ad-bie pee Hy 58 ssom" | 4098 | az bie bee 1 58 nism" | 208 | arbi pee ye seem" | 192, | sbi pee ye nism" | 4096 | az bie pee Hy a 2 ssom" | tesa | apie Peis iy a 2 nism" | 8192 | as-bie pee a 1 ssom" | 32768 | is-bie pee a 1 nism" | tesa | aap baie iy DOTLEN LULLED ALLELUIA LLL LTT TALLEST TELLTALE lone pncRo #1 SEE(TIEKDT), // Target BRAM, “1BKD" or T36KB™ DEVICE ("TSERIES"); // Target Device: "VIRTEXS™, “VIRTEXG", "SPARTANS", "7SERIES™ PoRES(O), // optional output register (0 oF 2) BNET (36"R000000000),// Initial values on curput pore INET_FELE (OHONE), WRITEREDTH(O), //" Valid values are 1-12 (37-72 only valid when BRAM Sr2E-"36xb" READLNIDTH(O),| // Valid values are 1-72 (37-72 only valid when BRAM.SIZEW" 36K" SRVAL(36"RO00000000), // Set/Rezet value for pore output WRITE_MODE (TWRITE_PIRGT"), // WRITE FIRST", "READLPIRST", oF *HO_CHANGE" 12700 (256"0000000000900000000000000G00000000000000000000000000000000000000) 3127_01 (256"m0000000000900000000000000G00000000000000000000000000000000000000) , 3127_02 256"m0000000000900000000000000G00000000000000000000000000000000000000) , 103 (256"n00000000000000000000000000000G0000000000000000000000000000000000), Dg (256"n00000000000000000000000000000G0000000000000000000000000000000000), 05 (256"n0000000000000000000000000000000000000000000000000000000900000000) "06 (256"n00000000000000900000000000000G0000000000000000000000000000000000), 107 (256"n0000000000000000000000000000000000000000000000000000000000000000) , bg (256 noDooooDoDoo¢osoo0o¢oNUNGCBBOGDGDODDUOUDDDDBODDDDDBODDDeG0000000), 109 (256"n00000000000000000000000000000G0000000000000000000000000000000000), 1x (256"h0000000000000000000000000000000000000000000000000000000900000000) “be (256"n00000000000000000000000000000G0000000000000000000000000000000000), De (256"n000000000000000000000000G000000G000000G0000000000000000000000000), 1p (256"n00000000000000000000000000000G0000000000000000000000000000000000), 3127_0e {256"h0000000000900000090000000G0000000000000G000000000000000000000000) 3127_0F (256"h0000000000900000000000000G00000000000000000000000000000000000000) , 3127_10 (256 "h0000000000900000000000000G0000000000000G000000000000000000000000) , 3127-11 (256"m000000000090000000000000000000000000000G000000000000000000000000) , 3127-12 (256"h0000000000900000000000000000000000000000000000000000000000000000) , 1256 "m0000000000900000000000000000000000000000000000000000000000000000) , ‘41256 "m0000000000900000000000000Gd0000000000000000000000000000000000000) , ' (256 "h0000000000900000000000000G00000000000000000000000000000000000000) , 6 1256 "m0000000000900000000000000G00000000000000000000000000000000000000) , 7 1256 "m0000000000900000000000000G00000000000000000000000000000000000000) , 8 1256 "m0000000000900000000000000Gd0000000000000000000000000000000000000) , '9 1256 "m0000000000900000000000000000000000000000000000000000000000000000) , a (256"80000000000000000009000000000000000000000G00000000000000000000000) , '8 (256 "m0000000000900000000000000000000000000000000000000000000000000000) , 3 (256000000000 0000000¢09000000000000000000000000000000000000000000000) (256 "h0000000000900000000000000G00000000000000000000000000000000000000) , £256 "m0000000000900000000000000000000000000000000000000000000000000000) , (256 *m000000000090000¢0000000dGd0ed00000u000GN0ND00B00N000B0000000000) , Xilinx 7 Series FPGA Libraries Guide for HDL Designs 22 wwwxilinx.com UG76S (v 13.4) January 18, 2012© XILINX. Chapter 2: About Unimacros z1127_20 (256"0000000000900000000000000000000000000000000000000000000000000000) , 3127_21 (256"h0000000000900000000000000G0000000000000G000000000000000000000000) , 3127_22 (256"h0000000000900000000000000G0000000000000G000000000000000000000000) , 3127_23 1256"h0000000000900000000000000000000000000000000000000000000000000000) , 312724 (256"h000000000090000000000000000000G000000000000000000000000000000000) , 3127_25 (256"h0000000000900000000000000G00000000000000000000000000000000000000) , 312726 (256"h0000000000900000000000000000000000000000000000000000000000000000) , 3127_27 (256"h0000000000900000000000000G0000000000000G000000000000000000000000) , 3127_28 (256"h0000000000900000000000000G00000000000000000000000000000000000000) , 3127_29 (256 "h0000000000900000000000000000000000000000000000000000000000000000) , 3127 2a 256"h0000000000900000000000000G00000000000000000000000000000000000000) , 312728 256"h0000000000900000000000000G00000000000000000000000000000000000000) , 3127_2¢ (256 "h000000000090000000000000000000G000000000000000000000000000000000) , 12720 (256"h0000000000900000000000000G00000000000000000000000000000000000000) , 31272 (256"0000000000900000000000000G0000000000000G000000000000000000000000) , 3127_2F (256"h0000000000900000000000000G0000000000000G000000000000000000000000) , 3127_30 (256 "m000000000090000000000000000000G000000000000000000000000000000000) , 3127_31 (256"m0000000000900000000000000G0000000000000G000000000000000000000000) , 3127_32 (256"h0000000000900000000000000G00000000000000000000000000000000000000) , 3127_33 (256 "m0000000000900000000000000000000000000000000000000000000000000000) , 312734 1256 mooDoOoODoDoOooDdoo0o0UdUNGUBEOUOUDDUDUOUDDUDDODODDDDODDOCONONeNN) 3127_35 (256"h0000000000900000000000000G00000000000000000000000000000000000000) , 3127_36 1256"h0000000000900000000000000000e00000000000000000000000000000000000) , 3127_37 (256"m0000000000900000000000000G00000000000000000000000000000000000000) , 127_38 (256 "h0000000000900000000000000G00e00000000000000000000000000000000000) , 3127_39 (256 "m0000000000900000000000000000000000000000000000000000000000000000) , 127_3A 256"m0000000000900000000000000G00000000000000000000000000000000000000) , 127 38 256"h0000000000900000000000000000000000000000000000000000000000000000) , 3127_3¢ (256 "h0000000000900000000000000000000000000000000000000000000000000000) , 3127 _3p (256 "h0000000000900000000000000G00000000000000000000000000000000000000) , 127_3e (256"0000000000900000000000000000000000000000000000000000000000000000) , 3127_3F (256"h0000000000900000000000000G0000000000000G00uD00000000000000000000) , [) the next set of 12T xx are valid when configured az 36x 42740 (256"m0000000000000000000000000000000000000000000000000000000000000000) , 3127_41 (256"h0000000000900000000000000000000000000000000000000000000000000000) , 127 _42 (256"h000000000000000000000000000000000000000G000000000000000000000000) , 3127_43 (256"h0000000000900000000000000000000000000000000000000000000000000000) , 3127 _44 (256"h0000000000900000000000000000000000000000000000000000000000000000) , 3127_45 (256"0000000000900000000000000000000000000000000000000000000000000000) , 3127_46 (256"0000000000000000000000000000000000000000000000000000000000000000) , 3127_47 (256"h000000000090000000000000000000000000000G000000000000000000000000) , 3127_48 (256"0000000000900000000000000000000000000000000000000000000000000000) , 31z7_49 (256 "0000000000900000000000000000000000000000000000000000000000000000) , 174A 256 "mooDoOo0DoD90o00000090U0UNGUBEoUDUDDUDUOUDDUDDOOODEDDODDOCONONeNN) 127_48 (256 "h0000000000900000000000000000000000000000000000000000000000000000) , 3127_4¢ (256"h0000000000900000000000000G00000000000000000000000000000000000000) , 127_4b (256 "h0000000000900000000000000000000000000000000000000000000000000000) , 3127_4e (256"0000000000900000000000000G00000000000000000000000000000000000000) , 3127_4F (256"0000000000900000000000000000000000000000000000000000000000000000) , 312750 (256 "h0000000000900000000000000G00000000000000000000000000000000000000) , 312751 (256"h0000000000900000000000000G00000000000000000000000000000000000000) , 3127 52 (256"h0000000000900000000000000G00000000000000000000000000000000000000) , 3127 53 1256"h0000000000900000000000000G00000000000000000000000000000000000000) , 312754 (256"h0000000000900000000000000G00000000000000000000000000000000000000) , 3127_55 (256"h0000000000900000000000000000000000000000000000000000000000000000) , 312756 256"h0000000000900000000000000000000000000000000000000000000000000000) , 3127_57 (256"h0000000000900000000000000G00000000000000000000000000000000000000) , 12758 (256"h0000000000900000000000000G00000000000000000000000000000000000000) , 312759 1256 "h0000000000900000000000000000000000000000000000000000000000000000) , 327 _5A{256"0000000000900000000000000G00000000000000000000000000000000000000) , 3127 58 256"h0000000000900000000000000000000000000000000000000000000000000000) , 3127_5¢ (256 "h0000000000900000000000000000000000000000000000000000000000000000) , 1275p 256"h0000000000900000000000000000000000000000000000000000000000000000) , 127_5e (256"0000000000900000000000000000000000000000000000000000000000000000) , 127 5F (256"0000000000900000000000000000000000000000000000000000000000000000) , 312760 (256"h0000000000900000000000000G0000000000000G000000000000000000000000) , 3127_61 (256"0000000000900000000000000000000000000000000000000000000000000000) , 127762 (256 "mooD00o0DoD90o00000090uNUdGUBEOUDUDDUDUOUDDUDDODODEDDODDOCONONeNN) 3127_93 (256"h0000000000900000000000000000000000000000000000000000000000000000) , 3127_4 (256"h0000000000900000000000000000000000000000000000000000000000000000) , 3127_95 256 "0000000000900000000000000000000000000000000000000000000000000000) , 127_66 1256 "h0000000000900000000000000G000000000N000G00ND00000000000000000000) , Xilinx 7 Series FPGA Libraries Guide for HDL Designs UG76S (v 13.4) January 18, 2012 wewwaxllinx.com 23XILINX. n0000000000900000000000000000000000000000000000000000000000000000), h000000000s900090000000G00000dG000000G000000000000000000900000000), h000000000s900090000000G00000dG000000G000000000000000000900000000), h000000000s900090000000G00000dG000000G000000000000000000900000000), h000000000s900090000000G00000dG000000G000000000000000000900000000), h000000000s900090000000G00000dG000000G000000000000000000900000000), h000000000s900090000000G00000dG000000G000000000000000000900000000), h000000000s900090000000G00000dG000000G000000000000000000900000000), h000000000s900090000000G00000dG000000G000000000000000000900000000), h000000000090e090000000Gd00a0dG000000G000000000000000000000000000), h000000000s900090000000G00000dG000000G000000000000000000900000000), h000000000s900090000000G00000dG000000G000000000000000000900000000), h000000000s900090000000G00000dG000000G000000000000000000900000000), h000000000s900090000000G00000dG000000G000000000000000000900000000), h000000000s900090000000G00000dG000000G000000000000000000900000000), h000000000s900090000000G00000dG000000G000000000000000000900000000), h000000000s900090000000G00000dG000000G000000000000000000900000000), h000000000s900090000000G00000dG000000G000000000000000000900000000), h000000000s900090000000G00000dG000000G000000000000000000900000000), h000000000090¢090000c00ad00a0dG0000000000000000000000000000000000), hoooo0 oDooseseos0o90¢0NGd0daudG0GDDBDUOUDDEDDOODDEDDODDDeGNGN0000) h000000000s900090000000G00000dG000000G000000000000000000900000000), h000000000s900090000000G00000dG000000G000000000000000000900000000), h000000000s900090000000G00000dG000000G000000000000000000900000000), (256 "m0000000000900000000000000Gd0edG00N0UDU0GNDUDDDDDDDDDDDDOGONGNRNN} , 50 (256" noD000000090000000090000000000G0000000000000000000000000000000000), 2 1256 "movDo0o000090990¢090o000U0GN0e0G0GN0NDU0GN0NDNDB0DDDDDDADC0N0N000) , 102 (256" n00000000090000000000000000000G0000000000000000000000000000000000), 103 (256" n000000000900000000000NG0G0000G0000000000000000000000000000000000), Dg (256" n000000000900000000000NG000000G00000D0000000000000000000000000000), 105 (256" n0D0000000900000000000N00G0000G0000000000000000000000000000000000), 10g (256" n0D0000000900009000000NG0G0000G00N00DG00ND0D000000D00000000000000), 107 (256"h0D0000000900e09000000dGdc000dG00NDUDG0UNDUDS0DDDDDBDDDONGN000000), 18 (256" noD0000000000000000000NG0G0000G0000000000000000000000000000000000), 109 (256" n0D0000000900000000000NG000000G000000000N000000000000000000000000), 1x (256" h00000000090000000000000000000G0000000000000000000000000000000000), 1p (256" n000000000900000000000NG000000G0000000000000000000000000000000000), De (256" h000000000900000000000NG000000G00000DG000D0DB00000000000000000000), 1p (256" n000000000900000000000NG000000G00N00DG00NND000000000000000000000), De (256" n000000000900000000000000G0000G0000000000000000000000000000000000), Dr (256" noDooooDoDeooeosooooeUDUOGUBEoUDUDDUDUOUDDUDBODODEDBODDOCONONeNO} (SEE_BACRO_inst ( (BO) 77 output data, width defined by READ_WzOTH p: ADDR(ADDRI, // Input address, width defined by read/write po cukicne), | // Iebit input clock BE IDE), Ve tnput data port, width defined by WRITE WIDTH parameter EN) Y) Libis Sapae! maw enable RESCE(RESCE), // I-bit input output register enable REIRSH], | // Tobit input reset ME (RE (i toput write enable, width defined by write port depth bs 11 end of BRAM SINGLE WACRO_inct instantiation For More Information See the 7 series FPGA User Documentation (User Guides aud Data Sheets) Xilinx 7 Series FPGA Libraries Guide for HDL Designs 24 wwwxilinx.com UG76S (v 13.4) January 18, 2012£ XILINX: Chapter 2: About Unimacros BRAM_TDP_MACRO Macro: True Dual Port RAM Introduction 7 series FPGA devices contain several block RAM memories that can be configured as general-purpose 36kb or 18kb RAM/ROM memonees. These block RAM memories offer fast and fleable storage of large amounts of on-chip data Both read and wnite operations are fully synchronous to the supplied clock(s) of the component. However, READ and WRITE ports can operate fully independently and asynchronous to each other, accessing the same memory aay. Byte-enable wnte operations are posable, and an optional output register can be ‘used to reduce the clock-to-out times of the RAM. Port Description Name Direction | Width Function DOA Outpt | See Configuration Tale | Dee output us addzesed Wy ADDRA DOB Outpt [See Configuration Table | Date output bus addressed by ADDI DIA Taps Seg Condgaration ble [Patanput bar addeeed by ADDN DIB Taps Seg Condgaration Te [Patnput bar aldreved by ADDN Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www xilinx.com 25Chapter 2: About Unimacros £ XILINX: Name Direction | Width Function ‘ADDRA ADRS [lapst | See Contguinton Table | Addhevsinpat buses fos Fon A B WEA WEB Tepet__ [Sep Conguatin Tie | Wits mublefor Pon AB ENA ENB iat [tl WiiteRead enables for Part AB RSTA RST impatt Oniput registers synchronous reset fr Pon AB TEGCEAREGCED [input [1 Output register dock enable input for Part A.B (aid culy wher DO.REGH) GA Ce iat | WiiteRRead dock input for Pat AB Port Configuration ‘This unimacro is aparametenizable version of the primutive, and can be instantiated only. Use this table to correctly configure the urumacro to meet design needs WRITE_WIDTH_AIB- | READ_WIDTH_A'B- DIADIE DOA/DOB BRAMSIZE | ADDRA/B WEAB 36-19 19 35 10 4 1610 a 3-5 2 as 5 2 ry 7 5 16-10 %19 Bak a 1610 a 3-5 2 Ts 5 2 1 7 5 a8 3619 Bak 2 7 1610 2 3-5 2 ns 5 2 1 7 5 1s 3619 Bak 5 7 1610 5 35 5 a 5 2 1 7 5 Xilinx 7 Series FPGA Libraries Guide for HDL Designs 26 woww.xitinx.com UG76E (v 19.4) January 18, 2012£ XILINX: Chapter 2: About Unimacros WRITE_WIDTH_A/B- READ_WIDTH_A/B- DIADIB DOA/DOB BRAM SIZE ADDRAB WEAB 2 3619 36K i 1 1810 1 9-5 uy 43 uw 2 uw 1 15 1 3619 36K 15 1 1610 15 9-5 6 43 15 2 15 1 15 7840 16:0 18K 10 9-5 u 43 2B 2 8 1 u 9-5 16:0 18K u 7 1m 2B 8 1 uw 3 18:10 18K 2 1 o-5 2 43 2B 2 8 1 uw 2 18:10 18K 3 1 9-5 3 18 8 1 uw 1 18:0 18K uw 1 9-5 i 43 1 uw 1 uw Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www. 2Chapter 2: About Unimacros £ XILINX: Design Entry Method ‘This unimacro is aparameterizable version of the primitive, and can be instantiated only. Consult the Port Configuration section to cormectly configure this element to meet your design needs. Tnvtantiation Yer Tnference Ne CORE Gemerater™ and winards Ne Waco apport Recommended Available Att: Attribute(s) Type Allowed Values | Default | Description BRAM SZE Sring SOKO" "18K" _| TSK Configures RAMas “S6Kb" or TOKO memory DEVICE Sring SERIES TSERIES | Target hardware ardutecture DO_REG Integer [0.1 0 “Avvalue of] enables to the output registers to the RAM enabling quicker dock-to-out from the RAMAat the expense of an added dock cyde of read latency. Avvalue of O allows a read in one dock eyde but will have slower dock to out timing INIT Hew. ‘Any 72Bit Value | Allzeror | Species the initial value on the output after deamal configuration INIT_FILE, Sring Sring NONE | Name of file containing initial wiles representing fle name and Tocation, READWIDTH, integer [1-72 36 ‘Species the size of the DI and DO buses ‘WRITE_WIDTH ‘The ollowing combinations are allowed © READ_WIDTH = WRITE_WIDTH ©) Wasymmetric. READ_WIDTH and WRITE_WIDTH must bein the ratio of2, or ist be values allowed by the unis (1,2, 48,9, 16,18, 52, 35) ‘SM_COLLISON_ | Sing "ALL! "ALL ‘Allows modification of the amulation behavior if CHECK "WARNING amemory collision occurs. The output is affected ONLY’ fae follows GENERATE_X. ERATE, © "ALL" Waming produced and affected NONE: cutpats/memory location gounknown 0), ‘© “WARNING_ONLY"- Warning produced and affected outputshmemory retain last value © "GENERATE_X_ONLY" - No warning. However affacied outputsinemary go unknown 0). © NONE" - No warming and affected outputs/memory retain last value Note Setting this toa value other than "ALL’ can allow problems in the design go unnoticed during simulation. Care should be taken when changing the value of this attubute Pleace see Xilinx 7 Series FPGA Libraries Guide for HDL Designs 28 wwwxilinx.com UG768 (v 13.4) January 18, 2012£ XILINX. Chapter 2: About Unimacros Attribute(s) Type Allowed Values | Default _ | Description Te Syitlasts ad Sora on Deg CHAE TOE OTE information SRVALA SRVALB [Hea ‘Any72Bit Value | Alleroes | Specifies the output value of on the DO port decimal upon the assertion of the synchronous reset (RST) signal INTO INTFF | Hea ‘Any256Bit Value | Allzeroes | Allows speaication of the initial contents ofthe decimal 16K) or S2Kb data memory array INTP_00 to Hea ‘Any256BH Value | Allaeroes | Allows speaiication of the initial contents ofthe INITP_OF decimal 2Kb or AK parity data memory aay VHDL Instantiation Template Unless they already exist, copy the following two statements and paste them before the entity declaration. Generic mop Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG76S (v 13.4) January 18, 2012Chapter 2: About Unimacros XILINX. 30 Xilinx 7 Series FPGA Libraries Guide for HDL Designs wwwxilinx.com UG76S (v 13.4) January 18, 2012© XILINX. Chapter 2: About Unimacros = eronpo000000000000000000000Ga90200GnB00000000000000000000000000000"), port aap ( Xilinx 7 Series FPGA Libraries Guide for HDL Designs UG76S (v 13.4) January 18, 2012 wewwaxllinx.com atChapter 2: About Unimacros XILINX. bs Verilog Instantiation Template 1) spas z0P_YACRO: True Dual Port RAM a T series 1) xitine uot tibrarics Guide, version 13.4 ALTLALLULILAD LULL LEUL ELLIE T LILLE TTELT ALLELE Wy ORALREOTH_A/B | BRANLSIZE. | RAM Depth | ADDRA/B widen | WEA/B width // a i a | w3eree | gaze | aonb wee yy a | Serer | 20aa | tbe bei 7 a [omer | toze | to-mse bei 7 a | were" | 098 | az bse bee iy a [omer | 20aa | tbse bee 17 a | w3erer | G102 | as mse bee 17 a [omer | g098 | az mse bee 17 a | w3erer | teseg | danse bee 17 a [omer | e102 | asmse bee 17 a 1 | w3erer | a27s@ | ascbse bee 17 a 1 [overt | leseg | aanse bee iy DLITENLLLILA LULL EA ELLL LILI TLAL ELEY LULLED BRAM_rDrsAcRO #1 BRANLSTZE(TLERD"), // Target BRAM: "1akb" of T36KET DEVICE (TTSERIES), // Target device: "VIRTEXS", “VIRTEXG", "SPARTANS", "TSERIES™ OALRES (0), Y) optional port A outpur register (0 Or 1) OBLRES (0) + Y) opeional pore 8 surpur register (0 oF 1) INET_A(36"H0000000), // Znstial values on pore A output port B(26"H00000000), // Initial values on port B output port (ONONE") EDTHLB (0); // Valid values are 1-36 (19-36 oni eHLCHECK (FALL), // Collision check enable “ALL, "WARNING_ONLY™, sRvAL_A(36"R00000000), // Set/Reset value for port A output SRVALLB(36°RO0000000); // Set/Reset value for port B output WRITEMODE_A("WRITE FIRST"), // TWRITE FIRST", TREAD_FIRST", oF NO_CHANGE WRITEMODELB("WRITELFIRSI"), // TURITELFIRST", "READLPIRST", oF NOLCHANGE" 127 00 (2567m000000000000000000000u0u000000G000000000000000000000000000000000) , 3127_01 (256"m0000000000900000000000000G00000000000000000000000000000000000000) , 3127_02 256"m0000000000900000000000000G00000000000000000000000000000000000000) , 3127_03 (256"m0000000000900000000000000000000000000000000000000000000000000000) , 312704 (256"m0000000000900000000000000G0000U00000000G000000000000000000000000) , 3127_05 (256"h0000000000900000000000000000000000000000000000000000000000000000) , 312706 256 "h000000000090000000000000000000000000000G000000000000000000000000) , 3127_07 (256"m0000000000900000000000000000000000000000000000000000000000000000) , De (256"n00000000000000000000000000000G0000000000000000000000000000000000), ps (256"n00000000000000000000000000000G0000000000000000000000000000000000), 1x (256"h00000000000000000000000000000G0000000000000000000000000000000000), De (256*n000000000000e000000000000000dG000000000ND0DB00000000000900000000), EDTHLA (0) // Valid values are 1-36 (19-36 only valid when SRAM SIZE-"35KD") oli when BRAMLSIZE—"36EE") TELMEDTH_A(O), /7 Valid valuer are 1-36 (19-36 only valid when BRAM SIZE-"35KD") TELMEDTHL(O); // Valid values are 1-36 (19-36 only valid when BRAMSIZEO"36KD") Xilinx 7 Series FPGA Libraries Guide for HDL Designs 32. wwwxilinx.com UG76S (v 13.4) January 18, 2012© XILINX. Chapter 2: About Unimacros z27_0¢ (256"20000000000900000000000000000000000000000000000000000000000000000) , 3127 _0p (256 "h0000000000900000000000000G0000000000000G000000000000000000000000) , 3127_0e {256"h0000000000900000000000000G0000G00000000G000000000000000000000000) , 3127_0F (256"h0000000000900000000000000G00000000000000000000000000000000000000) , 3127_10 (256 "h0000000000900000000000000G0000000000000G000000000000000000000000) , 3127-11 (256"m000000000090000000000000000000000000000G000000000000000000000000) , 3127-12 (256"h0000000000900000000000000000000000000000000000000000000000000000) , 3127_13 (256 "00000000 00900000000000000000000000000000000000000000000000000000) , 3127_14 (256"h0000000000900000000000000000000000000000000000000000000000000000) , 3127-15 (256"h0000000000900000000000000G00000000000000000000000000000000000000) , 3127-16 (256"h0000000000900000000000000000000000000000000000000000000000000000) , 3127_17 256 "h000000000090000000000000000000000000000G000000000000000000000000) , 3127_18 (256 "h0000000000900000000000000000000000000000000000000000000000000000) , 3127-19 1256 "h0000000000900000000000000G00000000000000000000000000000000000000) , 3127_1A 256 "h0000000000900000000000000000000000000000000000000000000000000000) , 3127_18 (256 "h0000000000900000000000000000000000000000000000000000000000000000) , 3127 1¢ (256 "m0000000000900000000000000G0000G00000000G000000000000000000000000) , 3127_1p (256"h000000000090000000000000000000G00000000G000000000000000000000000) , 31271 (256"h0000000000900000000000000000000000000000000000000000000000000000) , 3127_1F (256 "0000000000900000000000000000000000000000000000000000000000000000) , 31 7_20 256 "mooDoOooDoD9oooDooo0o0UDUDGUBEOUDUDDUDUOUDDUDBODODEDDODDOCGNONRNN) 3127_21 (256"h0000000000900000000000000G0000000000000G000000000000000000000000) , 3127_22 (256"h0000000000900000000000000G0000000000000G000000000000000000000000) , 3127_23 1256"h0000000000900000000000000000000000000000000000000000000000000000) , 312724 (256"h000000000090000000000000000000G000000000000000000000000000000000) , 3127_25 (256"h0000000000900000000000000G00000000000000000000000000000000000000) , 312726 (256"h0000000000900000000000000000000000000000000000000000000000000000) , 3127_27 (256"h0000000000900000000000000G0000000000000G000000000000000000000000) , 3127_28 (256"h0000000000900000000000000G00000000000000000000000000000000000000) , 3127_29 (256 "h0000000000900000000000000000000000000000000000000000000000000000) , 3127 2a 256"h0000000000900000000000000G00000000000000000000000000000000000000) , 312728 256"h0000000000900000000000000G00000000000000000000000000000000000000) , 3127_2¢ (256 "h000000000090000000000000000000G000000000000000000000000000000000) , 12720 (256"h0000000000900000000000000G00000000000000000000000000000000000000) , 31272 (256"0000000000900000000000000G0000000000000G000000000000000000000000) , 3127_2F (256"h0000000000900000000000000G0000000000000G000000000000000000000000) , 3127_30 (256 "m000000000090000000000000000000G000000000000000000000000000000000) , 3127_31 (256"m0000000000900000000000000G0000000000000G000000000000000000000000) , 3127_32 (256"h0000000000900000000000000G00000000000000000000000000000000000000) , 3127_33 1256"m0000000000900000000000000G00000000000000000000000000000000000000) , 3127_34 (256 "h0000000000900000000000000000000000000000000000000000000000000000) , 3127_35 (256"h0000000000900000000000000G00000000000000000000000000000000000000) , 3127_36 1256"h0000000000900000000000000000e00000000000000000000000000000000000) , 3127_37 (256"m0000000000900000000000000G00000000000000000000000000000000000000) , 312738 1256 "mooD0OooDoD9oo0oo09000uDUNGUBEOUDUDDUDUOUDDUDDODODEDDODDDCONONeNN) 3127_39 (256 "m0000000000900000000000000000000000000000000000000000000000000000) , 127_3A 256"m0000000000900000000000000G00000000000000000000000000000000000000) , 127 38 256"h0000000000900000000000000000000000000000000000000000000000000000) , 3127_3¢ (256 "h0000000000900000000000000000000000000000000000000000000000000000) , 3127 _3p (256 "h0000000000900000000000000G00000000000000000000000000000000000000) , 127_3e (256"0000000000900000000000000000000000000000000000000000000000000000) , 3127_3F (256"h0000000000900000000000000G0000000000000G00uD00000000000000000000) , [) the next set of 12T xx are valid when configured az 36x 42740 (256"m0000000000000000000000000000000000000000000000000000000000000000) , 3127_41 (256"h0000000000900000000000000000000000000000000000000000000000000000) , 127 _42 (256"h000000000000000000000000000000000000000G000000000000000000000000) , 3127_43 (256"h0000000000900000000000000000000000000000000000000000000000000000) , 3127 _44 (256"h0000000000900000000000000000000000000000000000000000000000000000) , 3127_45 (256"0000000000900000000000000000000000000000000000000000000000000000) , 3127_46 (256"0000000000000000000000000000000000000000000000000000000000000000) , 3127_47 (256"h000000000090000000000000000000000000000G000000000000000000000000) , 3127_48 (256"0000000000900000000000000000000000000000000000000000000000000000) , 3127_49 (256 "0000000000900000000000000000000000000000000000000000000000000000) , 3127_4a (256 "h0000000000000000000000000000000000000000000000000000000000000000) , 127_48 (256 "h0000000000900000000000000000000000000000000000000000000000000000) , 3127_4¢ (256"h0000000000900000000000000G00000000000000000000000000000000000000) , 31z7_4p (256 "0000000000900000000000000000000000000000000000000000000000000000) , 317-4 [256 "mooD0Oo0DoDo0o90o0o000UUOGUBEOUOUDDUDUOUDDUDDODODEDDODDDCONONeNN) 3127_4F (256"0000000000900000000000000000000000000000000000000000000000000000) , 312750 (256 "h0000000000900000000000000G00000000000000000000000000000000000000) , 312751 (256"h0000000000900000000000000G00000000000000000000000000000000000000) , 3127_52 (256 "m0000000000900000000000000G0000000N0N0000N0ND00000000000000000000) , Xilinx 7 Series FPGA Libraries Guide for HDL Designs UG76S (v 13.4) January 18, 2012 wewwaxllinx.com 33Chapter 2: About Unimacros XILINX. z127_53 (256"0000000000900000000000000000000000000000000000000000000000000000) , 312754 (256"h0000000000900000000000000G00000000000000000000000000000000000000) , 3127_55 (256"h0000000000900000000000000000000000000000000000000000000000000000) , 312756 256"h0000000000900000000000000000000000000000000000000000000000000000) , 3127_57 (256"h0000000000900000000000000G00000000000000000000000000000000000000) , 12758 (256"h0000000000900000000000000G00000000000000000000000000000000000000) , 312759 1256 "h0000000000900000000000000000000000000000000000000000000000000000) , 327 _5A{256"0000000000900000000000000G00000000000000000000000000000000000000) , 3127 58 256"h0000000000900000000000000000000000000000000000000000000000000000) , 3127_5¢ (256 "h0000000000900000000000000000000000000000000000000000000000000000) , 1275p 256"h0000000000900000000000000000000000000000000000000000000000000000) , 127_5e (256"0000000000900000000000000000000000000000000000000000000000000000) , 127 5F (256"0000000000900000000000000000000000000000000000000000000000000000) , 312760 (256"h0000000000900000000000000G0000000000000G000000000000000000000000) , 312761 (256"h0000000000900000000000000000000000000000000000000000000000000000) , 3127_62 (256 "h0000000000000000000000000000000000000000000000000000000000000000) , 3127_93 (256"h0000000000900000000000000000000000000000000000000000000000000000) , 3127_4 (256"h0000000000900000000000000000000000000000000000000000000000000000) , 3127_95 256 "0000000000900000000000000000000000000000000000000000000000000000) , 3427_66 (256 "h0000000000900000000000000000000000000000000000000000000000000000) , 312767 (256 "mooDoOooDoD90o0oo0o090UDUOGUBEOUOUDDUDUOUDDUDDODODEDDODDDCONONRNN) 127_68 (256"0000000000900000000000000000000000000000000000000000000000000000) , 4127_9 (256 "h0000000000900000000000000000000000000000000000000000000000000000) , 127A (256"h0000000000900000000000000000000000000000000000000000000000000000) , 127_8 256 "h0000000000900000000000000G00000000000000000000000000000000000000) , 1z7_s¢ (256"h0000000000900000000000000000000000000000000000000000000000000000) , 127_0 (256"h0000000000900000000000000000000000000000000000000000000000000000) , 3127s (256"h0000000000900000000000000000000000000000000000000000000000000000) , 127_oF (256"h0000000000900000000000000G00000000000000000000000000000000000000) , 3127_70 (256"m0000000000900000000000000G00000000000000000000000000000000000000) , 3127_71 (256"h0000000000900000000000000G0000G00000000G000000000000000000000000) , 3127_72 (256 "h0000000000900000000000000G0000000000000G000000000000000000000000) , 3127_73 1256 "h0000000000900000000000000G00000000000000000000000000000000000000) , 3127_74 (256 "m000000000090000000000000000000000000000G000000000000000000000000) , 3127_75 (256"0000000000900000000000000G00000000000000000000000000000000000000) , 3127_76 (256"m0000000000900000000000000G00000000000000000000000000000000000000) , 3127_77 (256"h0000000000900000000000000G0000000000000G000000000000000000000000) , 3127_78 (256"h0000000000900000000000000000000000000000000000000000000000000000) , 3127_79 (256 "m000000000090000000000000000000000000000G000000000000000000000000) , 3127_7A 256"h0000000000000000000000000000000000000000000000000000000000000000) , 3127_7s 256"h0000000000900000000000000000000000000000000000000000000000000000) , 3127_7¢ (256 "m0000000000900000000000000G00000000000000000000000000000000000000) , 3127_7b 256"h000000000090000000000000000000G000000000000000000000000000000000) , 31277 (256"0000000000900000000000000000000000000000000000000000000000000000) , in27_7F {256 mooDoODoDoDoooe0s0o0o0UdUdGUBeOUOUDDUDUOUDDUDBODODEDEODDOCGTONeNN} J) the next set of 10rTPxe are for the parity bite uz7_#F (256"m0000000000900000000000000000000000000000000000000000000000000000) , 3427700 (256"h0000000000000000000000000000000000000000000000000000000000000000), 31z7F_01 (256"h0000000000000000000000000000000000000000000000000000000000000000), 31z7#_02 (256"n0000000000000000000000000000000000000000000000000000000000000000), 3127F_03 (256"n0000000009000000000000000000000000000000000000000000000000000000), 1z7F_0é (256"h0000000000000000000000000000000000000000000000000000000000000000), 3127F_05 (256"h0000000000000000000000000000000000000000000000000000000000000000), 3127F_06 (256"0000000009000000000000000000000000000000000000000000000000000000), z127F_07 (256"h00000000000000900000000000000G0000000000000000000000000000000000) , J the nent set of 1NrTPax are valid when configured a2 26K uz7#_08 (256" n000000000900000000000000G0000G0000000000000000000000000000000000), 3127F_09 (256"n0000000000000000000000000000000000000000000000000000000000000000), 31z7F_0a (256"h0000000000000000000000000000000000000000000000000000000000000000), 3127F_0e (256"n0000000009000000000000000000000000000000000000000000000000000000), i1z7F_0e (256"h0000000000000000000000000000000000000000000000000000000000000000), 3127#_0p (256"0000000009000000000000000000000000000000000000000000000000000000), 3127#_0e (256"n0000000000000000000000000000000000000000000000000000000000000000), 1z7#_DF (256"h0000000009000000000000000000000000000000000000000000000000000000), ) pha zoe wacRo_inee ( BOA (BOAT Vi Outpst port“ data, width defined by RERD_WIDTHA parameter Boe (poe) + W) Gutpse porte data, width defined by READ_MIOTHLD parameter ADDRAIADERAI, //) Input poet-A address, width defined by Port A depts ADDRBIADDRE), // Input port—B address, width defined by Port B depth Gika(euka)s | // Lobit. spot post-a clock Goe(euke), —// L-bit input pore-m clock Xilinx 7 Series FPGA Libraries Guide for HDL Designs 34 wwwxilinx.com UG76S (v 13.4) January 18, 2012XILINX: Chapter 2: About Unimacros pra tozal, U1 rnput port-k data, width defined by NRITE_MIDTHLA pi Bre (zB) + Y) input pores daca, width defined By NRE UA (ENR + Wy Libis Enpue pore-A enable Xe (ENE) Y) (opis input pore-b enable REGCEA(REGCER), // I-bit inpst pore-A surpur reg REGcED(REGcES); // I-bit inpst pore surpur reg RETA(RSTA); | // L-bit input pore-a eeses Rere(nare), —// L-bit input port-t roses EA (WER + Y) toput porta weite enable, width defined by F NEB (WEB) (input ports write enable, width defined By F hb 11 end of BRAMLTDP_YACRO_inst instantiation For More Information See the 7 series FPGA User Documentation (User Guides ard Data Sheets). Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG76S (v 13.4) January 18, 2012 www.xling.comChapter 2: About Unimacros £ XILINX: ADDMACC_MACRO Macro: Adder/Multiplier/Accumulator ADOMACC_ MACRO. ior TWesr Tb a reserseror mero PREADDA(WIOTH_PREADD-1}0] ee —Ppox ‘ADD MULTIPLY ROCUMULATO Introduction ADDMACC_MACRO simplifies the instantiation of the DSP48 block when used as apre-add, multiply accumulate function. It features parameterizable input and output widths and latency that ease the integration of DSP48 block into HDL. Port Description Name Direction | Width Function PRODUCT Ostpat | Vaniable width, equals the value of the WIDTH A atubute plus the value of the WIDTH B attnbute Primary data output PREADDI Tnpat ‘Variable, ee WIDTH PREADD | Preadder data mput attabute PREADD2 Tnpat ‘Variable, ee WIDTH PREADD | Preadder data mput| attabute ‘MULTIPLIER Tnpat Variable, see ‘Multiplier data input (WIDTH MULTIPLIER attribute CARRYIN Tapat 1 Cary input aK Tapat 1 Clok a Taupt 1 Clock enable LOAD Taput 1 Lead LOAD_DATA Input ‘Variable, see WIDTH PRODUCT | Ina DSP slice, when LOAD is asserted, loads P attubute with A'B+LOAD_DATA RST Input 1 Synchronous Reset Xx 7 Series FPGA Libraries Guide for HDL Designs. 36 wwwxilinx.com UG768 (v 13.4) January 18, 2012£ XILINX: Chapter 2: About Unimacros Design Entry Method ‘This unimacro is aparameterizable version of the primitive and can be instantiated only. Tnetantiation Yer Tnference Ne (CORE Generator™ and wisards Ne Maco support Recommended Available Attributes Attribute Type Allowed Values | Default Description WIDTH _PREADD Integer [1t028 ey Contrals the width of PREADDI and PREADD? inputs WIDTHMULTIPLIER [Integr [1tol8 18 Contrals the width of MULTIPLIER input ‘WIDTH PRODUCT Integer [1 toa 6 Contrals the width of MULTIPLIER contput LATENCY Integer [01254 3 ‘Number of pip line registers DEVICE ‘String ‘TSERIES °7SERIES “Target hardware ardutecure VHDL Instantiation Template Unless they already exdst, copy the following two statements and paste them before the entity declaration. Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www xilinx.com 37‘Chapter 2: About Unimacros € XILINX. bh Verilog instantiation Template J) npoUACC HRCRO? Variable wideh £ latency ~ Pre-Add -> multiplier —> Accumslate a Fonction implemented in = B5Pd8E a 1) xsnine woe Appuace pancRo #1 DEVICE ("7SERIES") , ERTENCY (4) uer PR (/ mace cesult output, width defined by WiOTH pRODUCT parameter CARRYEN(CARRYEN); —// I-bit carey-in input uk (cae + We (obit clock input CECE), (é (obit clock ensble input (¢ Lobit secumulater Lead input ao_pata); | "]/ kecumalacor load data input, width defined by WIDTH PRODUCT ER[GLTIPLTER), // Moltiplier daca input, width defined by WIDTH MULTIPLIER parameter PREADD2 (PREADD2), input, wideh defined by WISTH_PREADO parancter PREADDI (PREASDI) late input, wideh defined by NIDTHLPREADD parameter RET (RSE Y) Libis active high synchronous reset hb 1) end of RDDMACC_YACRO_inst instantiation For More Information See the 7 series FPGA User Documentation (User Guides ard Data Sheets). Xilinx 7 Series FPGA Libraries Guide for HDL Designs 38 wwwxilinx.com UG76S (v 13.4) January 18, 2012£ XILINX: Chapter 2: About Unimacros ADDSUB_MACRO Macro: Adder/Subtractor ADDSUB_MACRO. Sve a(moTes1-0) cannvour} — ‘ites — avosue —eannvin FESULT(WOTH:1)0);— —rer —ee —pax Introduction ADDSUB_MACRO simplifies the inst antiation of the DSP48 block when used as a simple adder/subtractor. It features paraneterizable input and output widths and latency that ease the integration of the DSP48 block into HDL. Port Description ‘Name Direction | Width (Bits) Function (CARRYOUT Outpt Carry Ont RESULT Output _| Vaniable, see WIDTH attmibute | Data output bus addresed by RDADDR, “ADDSUB Input 1 ‘When high, RESULTis an addition. When lov, RESULT ie a subtraction. A Taput Variable, see WiDTHatinbute | Data input toadd/sub B Taput Vanable see WiDTHattabute | Data input toadd/sub cE Tapat 1 Clock Enable ‘CARRYIN Taput 1 Canyln ak Tnpat 1 Clock RST Taput 1 Synchronous Reset Design Entry Method ‘This unimacro is aparametarizable version of the primitive and can be instantiated only. Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www xilinx.com 39Chapter 2: About Unimacros £ XILINX: Tnetantiation Yer Tnference Ne (CORE Generator™ and wisards Ne Maco support Recommended Available Attributes Attribute Type Allowed Values _ | Default Description DEVICE ‘String ‘7SERIES ‘7SERIES “Target hardware ardutecture LATENCY Integr [0.1.2 2 ‘Number of pip line registers, © 1-PREG: + 2. AREG=BREG= CREG: PREG WIDTH Integer 138) ro ‘AB, and RESULT port width, internal (customers can override B and RESULT port widths using other parameters WIDTHRESULT | Integer 138) ro TRerult part width overide. VHDL Instantiation Template Unless they already exdst, copy the following two statements and paste them before the entity declaration. Xilinx 7 Series FPGA Libraries Guide for HDL Designs 40 wwwxilinx.com UG768 (v 13.4) January 18, 2012© XILINX. Chapter 2: About Unimacros Verilog instantiation Template J) nposue_yncno: Variable width @ latency ~ Adder / subtrator implemented in = DsPdge a Tseries 1) xsnine woe fez Guide, version 13.4 AppsuB_MACRO #1 DEVICE (CTSERIES"), // Target Device: TVIRTEXSY, TVIRTEXG", "SPARTANS, ERTENCY (2) W) desired clock cycle latency, 0-2 wEDTH (48) Y) roput / oueput bug width, 1-48 RIA, (i Toput A bas, width defined by WIDTH parameter Anp_Sup(nos_sun), // "bit ada/sub input, high selects adi, low selects subtract BiB), Y) reput & bus, width defined by WIDTH parameter cARRVIN (CARVIN), // I-bit carey”in inpue ECE), (é Lobit clock enable input : Y) bie Glock inpue RET (RSE) 1) obit aetive high synchronous reset hb (11 f'n of ADDSUE_MACRO_inst instantiation For More Information See the 7 series FPGA User Documentation (User Guides ard Data Sheets). Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG76S (v 13.4) January 18, 2012 weww.xlline.com aChapter 2: About Unimacros £ XILINX: COUNTER_LOAD_MACRO Macro: Loadable Counter COUNTER LOAD_MACRO —rsr —fee —pox Introduction ‘oqwioTh_oara:1}0),mm COUNTER_LOAD_MACRO simplifies the instantiation of the DSP48 block when used as dynamic loading up/down counter. it features parametenzable output width and count by values that ease the integration of the DSP48 block into HDL. Port Description ‘Name Direction | Width Function 2 Output | Vaniable, see WIDTH_DATA | Counter output attribute oS Taput 1 Clock Enable cK Tapat 1 Clock LOAD Tapa Varable, see WIDTH_DATA | When asserted, loads the counter from attribute LOAD DATA (two-dodk latency) LOAD_DATA Tnput Varable, see WIDTH_DATA | Ina DSP alice arverting the LOAD pin will force attribute. this data into the P register wth a latency of 2 dogs DIRECTION Tnput 1 High for Up and Low for Down (toro-dock latency) RST Taput 1 Synchronous Reset Design Entry Method ‘This unimacro is aparameterizable version of the primitive, and can be instantiated only. 42 Tnetantiation Yer Inference Ne (CORE Generator™ and wisards Ne Maco suppart Recommended Xilinx 7 Series FPGA Libraries Guide for HDL Designs UG768 (v 13.4) January 18, 2012£ XILINX. Chapter 2: About Unimacros Available Attributes Attribute Type Allowed Values | Default Description DEVICE String SERIES SERIES “Target hardware architecture ‘COUNT BY Hea. “Any dBbit value | 000000000001 Count by, takes precedence over deamal WIDTH_DATA, WIDTHDATA [integer [148 8 Species counter width. VHDL Instantiation Template Unless they already exist, copy the following two statements and paste them before the entity declaration. bie up/down coun Verilog Instantiation Template 11 COUNTER 2OAD_YACHO? Loadable variable counter & a 7 Series 1) xsnine woe Guide, version 13.4 f2°h000000000001), // cou 11 end of COUNTER LOAD_HACRO_L For More Information See the 7 series FPGA User Documentation (User Guides aud Data Sheets) Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG76S (v 13.4) January 18, 2012Chapter 2: About Unimacros £ XILINX: COUNTER_TC_MACRO Macro: Counter with Terminal Count (COUNTER_TC_MACRO tof — —rsr auoaTa. wnoTtst)0) fm ‘Abts —bax Introduction COUNTER_TC_MACRO simplifies the instantiation of theDSP48 block when used as aterminal count, up/down, counter It Features parameterizable output width, termina count values, count by and count direction in order to ease the integration of DSP48 block into HDL. Port Description ‘Name Direction | Width (Bits) Function Tc Outpat a “Terminal count goes high when TC_VALUE is reached 2 Output | Vaniable, see WIDTH_DATA | Counter output attribute Taput 1 Clock Enable ak Tnpat 1 Clock RST Taput 1 Synchronous Reset Design Entry Method ‘This unimacro is aparametarizable version of the primitive and can be instantiated only. Tnvantiation Yer Tnference Ne CORE Gemerater™ and winards Ne ‘Macro support Recommended 44 Xilinx 7 Series FPGA Li wwwxilinx.com ries Guide for HDL Designs UG768 (v 13.4) January 18, 2012£ XILINX. Chapter 2: About Unimacros Available Att: Attribute Type Allowed Values _ | Default Description RESETUPONTC |Bocean | True False Falee ‘Species whether toreset the counter upon reaching terminal count DEVICE ‘Sing ‘7SERIES ‘TSERIES “Target hardware ardutecure DIRECTION ‘String "UP", DOWN” UP) Count up versus count down, COUNT_BY Hexa “Any 48 bit value | 000000000001 Count by n; taker precedence over decmal WIDTH_DATA, TC_VALUE Hea ‘Any iSbitvalue | Allzeros ‘Tenninal count value WIDTHDATA [integer [1-8 # ‘Species counter width VHDL Instantiation Template Unless they already exdst, copy the following two statements and paste them before the entity declaration. Verilog Instantiation Template Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG76S (v 13.4) January 18, 2012 www.Chapter 2: About Unimacros € XILINX: For More Information See the 7 series FPGA User Documentation (User Guides aud Data Sheets) Xilinx 7 Series FPGA Libraries Guide for HDL Designs 46 wwwxilinx.com UG768 (v 13.4) January 18, 2012£ XILINX: Chapter 2: About Unimacros EQ_COMPARE_MACRO Macro: Equality Comparator £0. COMPARE MACRO sms ATA. IN(WHOTH_OATA:1}0) —rsr ‘vibes —ee —bak Introduction EQ_COMPARE_MACRO simplifies the instantiation of the DSP48 block when used as an equality comparator. It features paramaenizable input and output widths, latencies, mask, and input sources that ease the integration of the DSP48 block into HDL. Port Description ‘Name Direction | Width Function 2 Outpat— [1 ‘Active High pattern detection. Detects match of DATA IN and the selected DYNAMIC _PATTERN gated by the MASK Rerult arves on the same cycle as P. DATA IN Tnput Variable wadth, equals the value | Input data tobe compared of the WIDTH attubute DYNAMIC PATTERN | input Variable wadth, equals the value | Dynamic data to be compared to DATA IN. of the WIDTH attubute cK Tnpat 1 Clock oS Tnupt 1 Clock enable. RST Tapat 1 Synchronous Reset Design Entry Method ‘This unimacro is aparameterizable version of the primitive, and can be instantiated only. Tnvantiation Yer Inference Ne CORE Generator and wisards Ne Macro support Recommended Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www xilinx.com a7Chapter 2: About Unimacros £ XILINX: Available Attributes Attribute Type Allowed Values | Default Description DEVICE Sting ‘Target hardware ardutecture ‘SEL_PATIERN Integer [11028 ey Contraly the width of PREADDI and PREADD? inputs MASK Hews ‘whe allzeros ‘Mack tobe ured for patter detector decmal ‘STATIC_PATTERN Hexa whee allzeros Pattern to be used for pattern decmal detector ‘SEL_MASK ‘Sing. "MAS, “MASE Selects whether to-uze the static “DYNAMIC_ MASK or the C input for themack PATTERN’ of the patter detector WIDTH Integer [1t048 6 ‘Width of DATA.IN and DYNAMIC_PATTERN. LATENCY Integer [0.12.3 2 ‘Number of pip line registers + 1 QREG=1 VHDL Instantiation Template Unless they already exdst, copy the following two statements and paste them before the entity declaration. Xilinx 7 Series FPGA Libraries Guide for HDL Designs 48 wwwxilinx.com UG768 (v 13.4) January 18, 2012© XILINX. Chapter 2: About Unimacros Verilog instantiation Template J) ea.SOMPARE MACRO: Equality Conparater implemented in 2 DePdeE a Tiseries 1) xsnine woe sez Guide, version 13.4 EQ_COMPARE MACRO 4( DEVICE ("TSERIES") + Target Device: "VIRTEXST, TVIRTEX6M, "7SERIES" ERTENCY (2), Desired clock cycle latency, 0 NASH (42"R000000000000), // Select bits ro be mazked, must sot SEL MASKA"HASK™ SEL MASK THASK"), SASK” = use NASH ters SEL PATTERN("STATIC_PATTERN"), // "STATICLPATTERN" ~ ze STATIC PATTERN parameter, -_PATTERN(48"H000000000000), // Specify static pattern, must set SEL PATTERN = "STATIC PATTERNT DEH (a8) Comparator curpur bus wideh, 1é8 PARE MACRO_inst ( Seek), // Lobit active high inpus clock enable fe), // obit positive edge clock snpue N(DRTALIN), // Input Date Suz, width determined by WIOTH p: PATTERN (DYNAMIC! PATTERN), // Tapur bynamic Match/Mask Bu 11 end of 29. COMPARE_YACRO_inst instantiation For More Information See the 7 series FPGA User Documentation (User Guides ard Data Sheets). Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG76S (v 13.4) January 18, 2012 weww.xlline.com 49Chapter 2: About Unimacros £ XILINX: MACC_MACRO Macro: Multiplier/Accumulator MACC_ MACRO. Sven B(QIOTH. 6:0) sms] LOAD_DATAUWIOTH 1:0) —roao ‘ites — avosue — carr Pawort Po) —rsr —ee —pax Introduction MACC_MACRO simplifies the instantiation of the DSP49 block when used in simple signed multiplier/accumulator mode It features parametenizable input and output widths and latencies that ease the integration of the DSP48 block into HDL. Port Description Name Direction | Width Function P Output | Vanable width, equals the value | Primary data output, of the WIDTH_A attnbute plas the value of the WIDTH B attribute A Tnput Variable, see WIDTH. A.attnbute, | Maluplier data input B Tnpat Variable, see WIDTH B attribute | Multiplier data input ‘CARRYIN Taput 1 Canyinput oS Taput 1 Clock enable cK Tapat 1 Clock LOAD Taupe 1 Load LOAD_DATA Input Vanuable width, equals the value | In a DS? alice, when LOAD is asserted, loads P ofthe WIDTH A sttnbute plas | with A'B+LOAD DATA, the value of the WIDTH B attribute Xilinx 7 Series FPGA Libraries Guide for HDL Designs 50 wwwxilinx.com UG768 (v 13.4) January 18, 2012£ XILINX: Chapter 2: About Unimacros ‘Name Direction | Width Function RST Tapat 1 Synchronous Reset “ADDSUB Tapa 1 High sets accumulator in addition mode, lov sets acounulatorin subtraction mode, Design Entry Method ‘This unimacro is aparameterizable version of the primitive, and can be instantiated only. Tnetantiation Yer Tnference Ne (CORE Generator™ and wisards Ne Maco support Recommended Available Attributes Attribute Type Allowed Values | Default Description DEVICE String SERIES SERIES “Target hardware architecture WiDTH_A Integer [14025 25 Contrals the width of Aimput WIDTH B Integer | 1tol8 8 Contrals the width of Binput LATENCY Integr [01234 3 ‘Number of pipeline registers + 1-MREG=1 and MREG Vand PRE + 4. AREG Land PRE VHDL Instantiation Template Unless they already exdst, copy the following two statements and paste them before the entity declaration. Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 5‘Chapter 2: About Unimacros € XILINX. hb Verilog instantiation Template J) wacesincRo: multiply Accumvlate Function implenented in = DSPAEE a T series 1) xsnine woe fez Guide, version 13.4 mace pace #1 DEVICE (TTSERIES), // Target Device: "VIRTEXSY, TVIRTEXG", "SPARTANS, "TSERIES™ Nev U W) desired clock cycle Iavency, 2-4 (i taiiplicr Avinput bus width, (i mattiplicr s-input bus width, Y) xeounslacor curpur bus width, RIA Hace input A busy width determined by WiOTH A: Aubsue(apnsus),// ivbit add/ssb input, high selects addy low selects subtract BiB), hace input ® busy width determined by saneter EARRYON(CARRYIN), // I-bit carry-in inpur ro accumulator CECE), // 1obit ative Righ input clock ensbie ELKIenE), // Lobie positive edge clock impure DAD (uOAS), // I-bit active high inpur load accumulator enable SRD_ORTA(LOAD_OATR), // Load accumulator input data, width determined by WIDTH? parameter REFIRSE]// 1-it input active high reser hb 1) end of uAce piNcRO_inst instantiation For More Information See the 7 series FPGA User Documentation (User Guides ard Data Sheets). Xilinx 7 Series FPGA Libraries Guide for HDL Designs 52 wwwxilinx.com UG76S (v 13.4) January 18, 2012£ XILINX: Chapter 2: About Unimacros MULT_MACRO Macro: Multiplier uct MACRO Sea B(MIOTH_B::09 “ibis —rsr —tce —bax Introduction PawoTH AnwoTH 61)0;mm MULT_MACRO simplifies the instantiation of the DSP48 block when used as a simple signed multiplier. It features parameterizable input and output widths and latencies that ease the integration of the DSPd8 block into HDL. Port Description ‘Name Direction | Width Function P Output | Variable width, equals the value | Primary data output of the WIDTH A attzbute plus the value of the WIDTH_B atinibute A Tnput Variable, see WIDTH. A.atinbute, | Maluplier data input B Tnpat Variable, see WIDTH B attribute | Multiplier data input Taput 1 Clock Enable ak Tnpat 1 Clock RST Taput 1 Synchronous Reset Design Entry Method ‘This unimacro is aparameterizable version of the primitive, and can be instantiated only. Tnvantiation Yer Tnference Ne CORE Gemerater™ and winards Ne ‘Macro support Recommended Xilinx 7 Series FPGA Libraries Guide for HDL Designs UG768 (v 13.4) January 18, 2012 wonwilinx.com 53Chapter 2: About Unimacros £ XILINX. Available Attributes Attribute Type Allowed Values _ | Default Description DEVICE ‘String TSERIES TSERIES “Target hardware ardutecure WIDTHA, Integer | 11025 2 Contrals the width of Asmput WIDTHB Integer | 1t018 18 Contrals the width of B input LATENCY Integer [0.12.54 3 ‘Number of pip line registers + 1-MREG=1 VHDL Instantiation Template Unless they already exdst, copy the following two statements and paste them before the entity declaration. Verilog Instantiation Template Xilinx 7 Series FPGA Libraries Guide for HDL Designs 54 wwwxilinx.com UG76S (v 13.4) January 18, 2012£ XILINX: Chapter 2: About Unimacros For More Information See the 7 series FPGA User Documentation (User Guides aud Data Sheets) Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www xilinx.com 55Chapter 2: About Unimacros £ XILINX: FIFO_DUALCLOCK_MACRO Macro: Dual Clock First-In, First-Out (FIFO) RAM Buffer FIFO _DUALGLOGK MACRO} Introduction FPGA devices contain several block RAM memories that can be configured as general-purpose 36 Kb or 18 Kb RAM/ROM memories. Dedicated logicin the block RAM enables you to easily implement FIFOs. The FIFO can be configured as an 18 Kb or 36 Kb memory. This unimacro configures the FIFO for using independent read and wnites clocks. Datais read from the FIFO on the rising edge of read clock and written to the FIFO on the rising edge of wnite dock. Depending on the offset between read and write clock edges, the Empty, Almost Empty, Full and Almost Full flags can deassert one cycle later. Due to the asynchronous nature of the clocks, the simulation modal only reflects the deassertion latency cycles listed in the User Guide Port Description ‘Name Direction Width Function ALMOSTEMPTY | Output 1 “Almost all valid entries in FIFO have been read ‘ALMOSTFULL Output 7 ‘Almost all enter in FIFO memory have been fled DO Output See Data output bus addressed by ADDR, Configuration, ‘Table below. EMPTY Output 1 FIFO i empty FULL Output 7 ‘All entries in FIFO memory are filled RDCOUNT Output See FIFO data read pointer Configuration ‘Table below. RDERR ‘Output 1 “When the FIFO is empty, any additional read op eration generates an error fag. 56 Xilinx 7 Series FPGA Libraries Guide for HDL Designs UG768 (v 13.4) January 18, 2012£ XILINX: Chapter 2: About Unimacros ‘Name Direction Width Function WRCOUNT Output See FIFO data write pater Configuration, ‘Table below. WRERR, Output 7 ‘When the FIFO ie full, any additional write operation generates an error flag DI Tnpat See Data input bus addressed by ADDR Configuration, ‘Table below. RDCLK Input 1 Clock for Read domain operation RDEN Tapat 1 Read Enable RST Tapet 7 “Asynchronous reset WRELK Tapat 1 Clock for Witte domain operation, WREN, Input 7 ‘Wiite Enable Port Configuration correctly configure the unimacro to meet design needs. ‘This unimacro is aparameterizable version of the primitive, and can be instantiated only. Use this table to DATA_WIDTH FIFO_SIZE WRCOUNT RDCOUNT Re 36Ky 9 9 3-19 36K 10 10 18K 9 9 18-10 36K u W 16K 10 10 35 36K 2 2B 16K WT T rr 36K 3 8 16K a Design Entry Method ‘This unimacro is aparameterizable version of the primitive, and can be instantiated only. Consult the Port Configuration section to correctly configure this element to meet your design needs. Tnetantiation Yer Tnference Ne CORE Generator and wicards Ne Maco support Recommended Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www xilinx.com ‘7Chapter 2: About Unimacros £ XILINX. Available Attributes Allowed Attribute Type Values Defauit _| Description ALMOSTEMPTY_|Hexadeamal | 155itValue | Allzeror | Setting determines the difference between OFFSET EMPTY and ALMOSTEMPTY conditions Mast be set using hexadecimal notation, ALMOSTFULL_ | Hexadeamal | 155Bit Value | Allzeror | Setting determiner the difference between OFFSET FULL and ALMOSTFULL condstions. Must be set using hevadeamal notation DATA_WIDTH Integer 1-72 4 ‘Width of DIDO bus. DEVICE ‘Saing. ‘TSERIES’ | TSERIES’ | Target hardware architecture, FIFO_SIZE ‘Suing. "BKB", "36K" | EK Configures the FIFO ar 18 Kb or 56 Kb menary, FIRST_WORD_ Boolean FALSE, TRUE [FALSE | If TRUE, the first word written into the empty FALL THROUGH FIFO appears at the FIFO output without RDEN asserted, VHDL Instantiation Template Unless they already exdst, copy the following two statements and paste them before the entity declaration. Xilinx 7 Series FPGA Libraries Guide for HDL Designs 58 wwwxilinx.com UG76S (v 13.4) January 18, 2012© XILINX. Chapter 2: About Unimacros Verilog instantiation Template J) erro DURLELOCK SACRO: Duel Clock First—tn, Pies a T series Wo xstine woe 2 Guide, version 13.4 out (F2¥0) RAM Buffer aa UIE, wit FIFOLSIZE | FIFO Depth | ROCOUNT/WRCOUNT widen // Io a a “eee | 2 ouare “ ssom" | 102d | 20-bse “ mem" | 512 | Subse “ ssom" | 2002 | nobis “ nism | tozd | 10-bse “ tiem" | tose | ike “ nism" | 2008 | robs “ ssom" | 8102 | iebse “ nism" | 2008 ike uw nue I UIE wt FIro_pUALELOCK pCR AunOST_EMPTY_OFFSET (9°00), // Sets AumogT_FULL OFFSET (9"R080),\ // Sets almost full threshold ERTALNEDTH(O), // Valid Values are 1-72 (37-12 oniy valid when FIF0_s12E—"36Kb") DEVICE (TTSERTES"), // Target device: "VIRTEXS", "VIRTEXS™, "TSERIES" FEFG_SIzE (T18RB"), // Target SRAM: TIERDM or 736KE FERST_WORD_FALL_THROUGH ("FALSE") // Sets the FIFO FRFT to "TRUE" of "FALSE" ) e1ro_DUALELOCKHAGROWinst ALMOSTENPTY (ALMOSTEMPTY), // 1-bit output almost enpty RIMOETFULLIALMOSTFULL), // 1-bit output almost full 2 (50) Ouepst data, width defined by OATANIDTH parameter erry (eer) , Tobie cucput empty FuLL(FUE + Tobie Gueput ful RBCOUNT (RDCCONT) » Ouepst read count, width determined by FIFO depth BERR [RDERR + Tobie ouput read error TREOUNT (HRCOINT) ouput write count, width determined by FIFO depth RERR [WRERR Tobie cucput write error BE (BE), Zope decay width defined by OATANIDTH parameter RocuK (REEL Bie Stat Feed eisck DEN (RDEN Tobit inpur read encble RETIREE), Tobit inpur reset RELK (ERED Tobit inpur rice clock REN (REN) T-bit inpur weiss enable bs 1) end of FIFO DURLCLOCK HACRO_inst instantiation For More Information See the 7 series FPGA User Documentation (User Guides ard Data Sheets). Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG76S (v 13.4) January 18, 2012 weww.xlline.com 59Chapter 2: About Unimacros £ XILINX: FIFO_SYNC_MACRO. Macro: Synchronous First-In, First-Out (FIFO) RAM Buffer woe agg NC MACRO Introduction [gpoournon morn FPGA devices contain several block RAM memories that can be configured as general-purpose 36Kb or 18Kb RAM/ROM memories. Dedicated logic in the block RAM enables you to easily implement FIFOs. The FIFO can be configured as an 18 Kb or 36 Kb memory. This urumacro configures the FIFO such that it uses one clock for reading as wall as writing Port Description Name Direction Width Function “ALMOSTEMPTY Output 1 ‘Almost all valid entries im FIFO have been read. “ALMOSTFULL Output 1 ‘Almost all ennesin FIFO memory have been DO ‘Output ‘See Configuration | Data output bus addressed by ADDR, Table EMPTY Output 1 FIFO i empty FULL Output 1 ‘All entries in FIFO memory are fled RDCOUNT Output See Configuration | FIFO data read painter ‘Table below. RDERR ‘Output 1 ‘When the FIFO is empty any additional read operation generates an error fag WRCOUNT ‘Output Sep Confewatien [FIFO data wate pointer WRERR Output 1 ‘When the FIFO is fll, any additional write operation generater an error lag. aK Input 1 Clock for Read/Wiite domain operation Xilinx 7 Series FPGA Libraries Guide for HDL Designs 60 wwwxilinx.com UG768 (v 13.4) January 18, 2012£ XILINX: Chapter 2: About Unimacros ‘Name Direction Width Function DI Tapat See Configuration | Data mput bus addressed by ADDR Table RDEN Input 1 Read Enable RST Tnpat 1 ‘Aryadurenous reset WREN Tnpat 1 Wiite Enable uration ‘This unimacro is aparameterizable version of the primitive, and can be instantiated only. Use this table to correctly configure the unimacro to meet design needs. DATA_WIDTH FIFO_SIZE WRCOUNT RDCOUNT 27 Ba 3 9 3-19 Ba 10 10 18K 3 9 18-10 eK Ht Ww 18K 10 10 35 eK 2 2 18K Wt Wt 14 eK 3 3 18K 2 2 Design Entry Method ‘This unimacro is aparameterizable version of the primitive, and can be instantiated only. Consult the Port Configuration section to correctly configure this element to meet your design needs. Tneantiation Yer Tnference Ne CORE Generator and wicards Ne Maco support Recommended Available Attributes Allowed Attribute Type Values Default | Description ALMOSTEMPTY_ [Headeamal |Any15Bit | Allzeros | Setting determines the difference between EMPTY OFFSET Value and ALMOSTEMPTY conditions. Must be set using hexadecimal notation. ALMOSTFULL_[Headeamal |Any15Bit | Allzeros | Setting determines the difference between FULL OFFSET Value and ALMOSTFULL conditions. Must be set using hexadecimal notation. DATA_WIDTH Integer 1-72 4 ‘Width of DIDO bus. DEVICE Suing ‘TSERIES’_ | 7SERIES'| Target hardware architecture DO_REG Binary or 1 DO_REG must be set to0 for lags and data to followa standard synchronous FIFO operation Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www xilinx.com 6Chapter 2: About Unimacros £ XILINX. ‘Allowed Attribute Type Values Default | Description ‘When DO_REGis set tol, effectively pipeline repister is added to the output of the synchronous FIFO. Data then has a one clock cyde latency However, the dosk-to-out timing is improved. FIFO SZ Sring TSK 56K [ISK _| Congres FIFO as 18Kb or SEK) memory, VHDL Instantiation Template Unless they already exist, copy the following two statements and paste them before the entity declaration. Pte SSrargee BRAM, T1EKE" or "36KE" Xilinx 7 Series FPGA Libraries Guide for HDL Designs 62 wwwxilinx.com UG76S (v 13.4) January 18, 2012© XILINX. Chapter 2: About Unimacros Verilog instantiation Template wen a 1) xsnine woe SYNC HACKO: Synchronous First—In, First-out ELL UIE, Firolstze {Piro bepeh | RocoUNt/ WR Sear | siz ssom" | 102d | mem" | 512 | ssom" | 2002 | nism | lozd | ssom" | 4008 | nism" | 2008 | ssom" | 8102 | nism" | 2008 nue I UIE wt Freo_smc_yacro_ #( SERIES"), // Target Device: "VIRTEXST, TVIRTEXGY, "TSERIES" OFFSET (9"HOGO), // Set the almost enpey th AumogT_FULL OFFSET (9"H080),\ // Sets almost full threshold DRIALNEDTH(O), // Valid values are 1-72 (37-12 only valid when FIFO_S1zE—"36Kb") POLREG(O), // Optional output register (0 oF 1) DASTZE’ (T1EKBM)”// Target BRAM! *1BKD" oF 736K" SYNC HACROLinet (| Sree Ty (aiHosTeMeTY) MLNOSTFULL (ALMOSTFULL) + 9 (Bo arse (eer) , (russ, NT (RDCOUNT) BERR [RDERR + TREOUNT (HRCOINT) RERR [ERERR Tobie cucput write error eux (ene + Tobie npur clock BIDE), Toput data, width defined by DATALNIDTE pat DEN (RDEN) + Tbe input read ensbie RETIREE) Tobit inpur reset REN (REN) T-bit inpur write enable bs 11 end of PrFO_svuc_UACRO_inct instantiation For More Information See the 7 series FPGA User Documentation (User Guides ard Data Sheets). Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG76S (v 13.4) January 18, 2012 www.xling.com64 Xilinx 7 Series FPGA Libraries Guide for HDL Designs wwwxilinx.com UG768 (v 13.4) January 18, 2012£ XILINX. Chapter 3 Functional Categories ‘This section categorizes, by function, the circuit design elements described in detal later in this guide. The elements (primitives and macros) ave listed in alphanumeric order under each functional category. Advanced Config/BSCAN Components Registers/Latches Arithmetic Functions JO Components ‘Sice/CLB Primitives Clock Components RAMROM Advanced Design Element Description XADC Primitive: Dual 12-Bit IMSPS Analog to Digital Converter Arithmetic Functions Design Element Description DSPIBEL Pranitive: 46-t Malti Functional Arithmetic Block Clock Components Design Element Description BUFG Prunitive: Global Clock Simple Buffer BUFGCE Prunitive: Global Clodk Buifer with Clock Enable ‘BUFGCE1 Primitive: Global Clock Buifer with Clock Enable and Output State 1 BUFGCTRE Prunitive: Global Clock Contral Butfer BUFGMOX Pranitive: Global Clock MUX Buiter BUFGMOX I Primitive: Global Clock MUX Bufer with Output Sate 1 BUFGMUX_CIRL Prunitive: 210-1 Global Clock MUX Buffer BUF Primitive: HROW Clock Buifer for a Single Clocking Region BUFHCE Primitive: HROW Clod: Bulfer for a Single Clocking Region with Clock Enable Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www xilinx.com 65Chapter 3: Functional Categories £ XILINX: Design Element Description ‘BUFO ‘Pranitive: Local Clock Buffer for 1/0 BUFR Prunitive: Malti Region Clock Buffer ‘BUFMRCE Prunitive: Malt: Region Clock Buffer with Clock: Enable BUFR Primutive: Regional Clock Buffer for I/O and Logic Resources within a Clock Region ‘MIMICME2_ADV, Prunitive: Advanced Mixed Mode Clock Manager ‘MMCME2_ BASE Prunitive: Bare Mixed Mode Clock Manager PLLE2 ADV Primutive: Advanced Phase Locked Loop PLL) PLLE2 BASE Primutive: Base Phase Locked Loop PLL) Config/BSCAN Components Design Element Description BSCANE2 Primitive Boundary San User Instruction CAPTURE? ‘Primitive Register Capture DNA PORT Primitive Device DNA Access Port EFUS_UR Primitive 52-bit non-volatile design ID FRAME ECE? Primitive: Configuration Frame Error Correction TCAPE2 Primitive: Intemal Configuration Access Part [STARTUPE2 Primitive. STARTUP Block UaR_ACCESSE Pranitive: Configuration Data Access VO Components Design Element Description DCIRESET Primitive: Digitally Controlled Imp edance Reset Component TBUF ‘Pranitive: Input Buffer IBUF_IBUFDISABLE Prunitive: Single-ended Input Buffer with Input Disable TBUF_INTERMDISABLE Prunitive: Sngle-ended Input Buifer with Input ‘Termination Disable and Input Disable TBUFDS: Prunitive: Differential Signaling Input Buffer TBUFDS_DIFF_OUT Prunitive: Differential Signaling Input Buffer With Differential Output IBUFDS DIFF_OUT Pranitive: Input Differential Buifer with Input Disable and _IBUFDISABLE Differential Output TBUFDS DIFF_OUT ‘Prinstive: Input Differential Buifer with Input Termination _INTERMDISABLE Disable, Input Disable, and Differential Output IBUFDS IBUFDISABLE Pranitive: Input Differential Buffer with Input Path Disable TBUFDS INTERMDISABLE ‘Prinative: Input Differential Buifer with Input Termination Disable and Input Disable TBUFG Prunitive: Dedicated Input Clock Butter 6s wwwxilinx.com Xilinx 7 Series FPGA Libraries Guide for HDL Designs UG768 (v 13.4) January 18, 2012£ XILINX: Chapter 3: Functional Categories Design Element Description TBUFGDS ‘Prunitive: Differential Signaling Dedicated Input Clock Buffer IBUFGDS_DIFF_OUT ‘Primitive: Differential Signaling Dedicated Input Clock Buffer with Differential Output TDELAYCTRL Primitive IDELAVEZ/ODELAYED Tap Delay Value Control DELAYED Primitive Input Fixed or Variable Delay Element INFIFO Primitive Input Firstin, Fist Out FIFO) TOBUF Primitive Bi-Direcional Batfer TOBUF_DCIEN Primitive: Bi Directional Sngle ended Buifer with DCland Input Disable TOBUF_INTERMDISABLE Prunitive: Bi Directional Single ended Buffer with Input ‘Termination Disable and Input Path Disable TOBUFDS Primitive: 3 State Differential Signaling 1/0 Buffer with ‘Active Lov Output Enable TOBUFDS_DCIEN Primitive: Bi-Darecional Differential Buffer with DCI Enable/Disable and Input Disable TOBUFDS_DIFF_OUT Pranitive: Differential Bi-directional Buffer wath Differential Output TOBUFDS DIFF_OUT_DCIEN ‘Pranstive: Br Diredional Differential Buffer with DCI Disable, Input Disable, and Differential Output TOBUFDS_DIFF_OUT -INTERMDISABLE ‘Primitive: Bi-Directional Differential Buffer with Input ‘Termination Disable, Input Disable, and Differential Output TOBUFDS_INTERMDISABLE ‘Prunitive: Bi Directional Differential Buifer with Input ‘Termination Disable and Input Disable ISERDESE2 Primutive: Input SERial/DESeralizer vith bitslip KEEPER Prunitive KEEPER Symbal OBUF, Pranitive: Ontput Buffer OBUFDS Primitive: Differential Signaling Output Buffer OBUFT Primitive: 3 State Output Buifer wath Active Low Output Enable OBUFIDS Pranitive:5-State Output Buifer with Differential Signaling, ActiveLow Output Enable ODELAYE? Pranitive: Output Faced or Variable Delay Element OSERDESE2 Primutive: Output SERial/DESenalizer with bitalip OUTFIFO Pranitive: Output Fire-in, First Out IFO) Buiter PULLDOWN, Primitive: Resistor to GND for Input Pads, Open-Drain and 5-State Outputs PULLUP Prunitive: Resistor to VCC for Input PADz, Op en-Drain, and 5-State Outputs Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www xilinx.com 67Chapter 3: Functional Categories £ XILINX: RAM/ROM Design Element Description FIFOLSEL Primitive: I6Kb FIFO (Fist-In-First-Out) Block RAM Memory FIFOSSEL Primutive: 36Kb FIFO (Fst In-First-Out) Block RAM Memory RAMI26XID Prunitive: 126-Deep by] Wide Dual Port Random Access ‘Memory (Selet RAM) RAMBSGXIS Prunitive: 256-Deep by l-Wide Randan Access Memory (Geleat RAM) RANSOM Prunitive: 52-Deep by Obit Wide Malti Port Random “Access Memory (sleet RAM) RANE2XID Primitive: 52:Deep byl Wide StatieDual Port Syndironous RAM RANB2XIS Prunitive: 52:-Deep by l-Wide Static Synchronous RAM RANERXIS] Primitive: 52.Deep by 1- Wide Static Syadironous RAM swith Negative Edge Clock RANB2OS Primitive: 32:Deep by2-Wide Static Synchronous RAM RAMBIM. Prunitive: 64: Deep by 4-bst Wide Malt Port Random “Access Memory (sleet RAM) RAMEEXID ‘Primitive: 6&-Deep by 1- Wide Dual Port Static Synchronous RAM RAMBUS Prunitive: 6L-Deep by -Wide Static Synchronous RAM RAMBAXISI Prinitive: 6 Deep by 1-Wide Static Syadironous RAM with Negative Edge Clock RAMBIGEL Pranitive: 18K-bit Configurable Synchronous Block RAM RAMBS6EL Prunitive: 36K-bit Configurable Syachronows Block RAM ROMI26x1 Prunitive: 126-Deep by 1-Wide ROM ROMBSEXT Primitive: 256-Deep by l-Wide ROM RONBIXI Primitive: 32-Deep by 1 Wide ROM ROME Primitive: 6: Deep by 1 Wide ROM Registers/Latches Design Element Description FDCE Primitive: D Flip-Flop with Clock Enable and ‘Asynchronous Clear FDPE Primitive: D Flip-Flop with Clock Enable and “Asynchronous Preset DRE ‘Primitive: D Flip-Flop with Clod: Enable and Syachronous Reset FDS ‘Prunitive: D Flip-Flop with Clod: Enable and Syacronous Set DDE Prunitive: Input Dual Data-Rate Register WDR_2CLK Prunitive: Input Dual Data Rate Register with Dual Clock Inputs 63 Xilinx 7 Series FPGA Libraries Guide for HDL Designs wwwxilinx.com UG768 (v 13.4) January 18, 2012£ XILINX: Chapter 3: Functional Categories Design Element Description DCE Prunitive: Transparent Data Latch with Asynchronous Clear and Gate Enable LDPE Primitive: Transparent Data Latch with Asynchronous Preset and Gate Enable ODDR Primitive: Dedicated Dual Data Rate DDR) Output Register, Slice/CLB Primitives Design Element Description CARRYS Primitive: Fast CarryLogicwith Look Ahead CPGLUTS Prunitive: Sanput Dynamically Reconfigurable Look-Up Table LUT) LT Prunitive: Bit Look-Up Table with General Output LoT_D Prunitive: Bit Look-Up Table with Dual Output LOT Primitive: I-Bit Look-Up Table with Local Output LUT Prunitive: 2Bit Look-Up Table with General Output Lud Prunitive: 2-Bit Look-Up Table with Dual Output WR Primitive: 2 Bit Look-Up Table with Local Output LoS Pranitive: 3Bit Look-Up Table with General Output LUD Prunitive: 3 Bit Look-Up Table with Dual Output LUTE Prunitive: 3 Bit Look-Up Table wath Local Output LUT Primitive: 4 Bit Look-Up Table with General Output ToT Prunitive: 4 Bit Look-Up Table with Dual Output LUTE Prunitive: 4 Bit Look-Up Table with Local Output LOTS Prunitive: SInput Lookup Table with General Output LUTE_D Primitive: Slnput Lookup Table with General and Loaal Outputs LUTEL Prunitive: SInput Lookup Table with Local Output LOTS Prunitive: 6Input Lookup Table with General Output LUTE 2 Primitive: Socinput, 2output, LookUp Table LUT Pranitive: GInput Lookup Table with General and Losal Outputs LUTEL Prunitive: 6Input Lookup Table with Local Output MOT Primitive: 2to-1 Look-Up Table Maltiplecer with General Output MIXED Primitive: 240] Look Up Table Maltiplexer with Dual Output MOXFT_L Pranitive: 240 look-up table Multiplexer wath Local Output MONS Prunitive: 2to-1 Look-Up Table Multiplecer with General Output Xilinx 7 Series FPGA Libr UG768 (v 13.4) January 18, 2012 jes Guide for HDL Designs www xilinx.com 69Chapter 3: Functional Categories £ XILINX: Design Element Description MOXFE_D Pranitive: 2101 Look Up Table Multiplexer with Dual Output MOXFE_L Pranitive: 2401 Look-Up Table Maltiplecer with Local Output SRLIGE Primitive: 16.Bit Shift Register Look-Up Table LUT) with Clock Enable SRLGE Primitive: 32 Clock Cyd, Variable Length Shaft Register Look-Up Table (LUT) with Clock Enable 70 Xilinx 7 Series FPGA Libraries Guide for HDL Designs wwwxilinx.com UG768 (v 13.4) January 18, 2012£ XILINX. Chapter 4 About Design Elements ‘This section describes the design elements that can be used with this architecture. The design elements are organized alphabetically. ‘The following information is provided for each design element, where applicable + Name of element + Brief deserption + Schematic symbol (if any) + Logic table (if any) + Port deseiptions + Design Entry Method + Available attributes (if any) + Example instantiation code + Formore information Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www xilinx.com nChapter 4: About Design Elements £ XILINX: BSCANE2 Primitive: Boundary-Scan User Instruction Introduction ‘This design cement allows access to and from intemal logic by the JTAG Boundary Scan logic controller This allows for communication between the intemal running design and the dedicated TAG pins ofthe FPGA. Each instance of this design element will handle one TAG USER instrichon (USER through USERA) as set with the JTAG_CHAIN attsbute, To handle al four USER instructions instantiate four of these elements and set the JIAG_CHAIN attsbute appropriately. Note thet for specific information on boundary sean for an architecture, see the Configuration User Guide for the specific device Port Descriptions Port Type Width | Function CAPTURE Outpt CAPTURE oaipat fom TAP controller DRCK Output‘ Gated TCK output, When SEL is asserted, DRCK toggles when CAPTURE or SIFT are asserted TESST Capt it Reset output for TAP contraller RUNTEST Oupat|t Output asserted when TAP contraler isin Ran Tete tate = Oupat ‘| USER instruction active oulpat srr Oupat|t SHIFT output fom TAP contraller TK Oupat ‘| Test Clock outpat, Fabric conection fo TAP Clock pin I Outpt Test Data input (DI) output from TAP conivaller Do Input 7 Test Data Output (DO) input for USER Fancton 7s Cup [t Test Mode Selec ouipat. Fabri connedtion to TAP UPDATE Oupat ‘| UPDATE output rom TAP contraller Design Entry Method Tavantiation Recommended Trference Ne CORE Generator and wisards Ne Maco sppat Ne Xilinx 7 Series FPGA Libraries Guide for HDL Designs n wwwxilinx.com UG768 (v 13.4) January 18, 2012© XILINX. Chapter 4: About Design Elements Available Attributes Attribute Type Allowed Values _| Default Description TTAGCHAIN [Deamal [1254 1 Value for USER command, VHDL Instantiation Template Unless they already exist, copy the following two statements and paste them before the entity declaration. generic mop ( ; cor us de vetuees 1 port map ( RUNTEST -> RUNTEST, —- I-bit output: Output asserted when TAP controller iz in Run Test/tdle state. zor, output, Data Input (FDI) output from TAP controller put: Test Data Output (FDO) input fo: Verilog instantiation Template J) sscaue2: Boundary-Sean User Instruction a Tse: 1) xsnine aoe BocaNE2 +1 HRIW(2) // Value for USER command. Possible values! 1-4 (CAPTURE), // I-bit output: CAPTURE output from TAP con REM (BRCE Y) Lobit output: Gated Tck output. when SEL (0 SHIFT are azcerved RESET (RESET), // RUNTEST (RUNTEST) 7 SEL (SEL) “ SRIT), 77 “I “ Sutput: Tear Clock output. Fabric connection to TAP Clock pin Or (ZBE) +, “ Gstput: Zest Sata input (For) output from TAP controller sas (2) “ © Node Select output. Fabric connection ©o TAP UPDATE (UPDATE), // w eta output (TDs) input for USER function hb 1) end of BSCANEZ inst instantiation ted when TAP contesiler is in Run Test/idle state Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG76S (v 13.4) January 18, 2012 www xilinx.comChapter 4: About Design Elements £ XILINX: For More Information See the 7 series FPGA User Documentation (User Guides aud Data Sheets) Xilinx 7 Series FPGA Libraries Guide for HDL Designs 74 wwwxilinx.com UG768 (v 13.4) January 18, 2012€ XILINX. Chapter 4: About Design Elements BUFG Primitive: Global Clock Simple Buffer eure ps Introduction ‘This design element is ahigh-fanout buffer that connects signals to the global routing resources for low skew distibution of the signal. BUFGs are typically used on clock nets as well other high fanout nets like sets/resets and dock enables Port Descriptions Port Type Width’ Function 1 Input 1 Clock input ° Output 1 Clock output Design Entry Method Tnvantiation Yer Tnference Recommended CORE Generator and wisards Ne Maco support Ne VHDL Instantiation Template Unless they already exdst, copy the following two statements and paste them before the entity declaration. Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www xilinx.com 5Chapter 4: About Design Elements £ XILINX. Verilog Instantiation Template For More Information See the 7 series FPGA User Documentation (User Guides aud Data Sheets) Xilinx 7 Series FPGA Libraries Guide for HDL Designs 6 wwwxilinx.com UG768 (v 13.4) January 18, 2012€ XILINX. Chapter 4: About Design Elements BUFGCE Primitive: Global Clock Buffer with Clock Enable Introduction ‘This design clementis a global clock buffer with a single gated input. Its O output is "0" when clock enable (CE) isLow (inactive). When lock enable (CE) is High, the I input is transferred to the O output. Logic Table Inputs ‘Outputs U cE ° x 0 0 1 1 1 Design Entry Method Tnetantiation Yer Inference Ne (CORE Generator™ and wisards Ne Maco support Ne VHDL Instantiation Template Unless they already exdst, copy the following two statements and paste them before the entity declaration. Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012Chapter 4: About Design Elements £ XILINX. Verilog Instantiation Template For More Information See the 7 series FPGA User Documentation (User Guides aud Data Sheets) Xilinx 7 Series FPGA Libraries Guide for HDL Designs 78 wwwxilinx.com UG76S (v 13.4) January 18, 2012€ XILINX. Chapter 4: About Design Elements BUFGCE_1 Primitive: Global Clock Buffer with Clock Enable and Output State 1 pe aurece1 Introduction ‘This design clement is amultipleced global clock buffer with a single gated input. Its O output is High (1) when lock enable (CE) is Low (inactive). When clock enable (CE) is High, the linputis transferred to the O output. Logic Table Inputs Outputs 1 cE ° x ° T T 1 T Port Descriptions Port Type Width Function T Tap T Clock buffer input « Imp 7 Cloak enable input ° Output 1 Closk buffer output Design Entry Method Tnetantiation Yer Tnference Recommended (CORE Generator™ and wicards Ne Maco support Ne VHDL Instantiation Template Unless they already exdst, copy the following two statements and paste them before the entity declaration. Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www. inx.com 79£ XILINX. Chapter 4: About Design Elements Verilog Instantiation Template For More Information See the 7 series FPGA User Documentation (User Guides aud Data Sheets) Xilinx 7 Series FPGA Libraries Guide for HDL Designs 80 wwwxilinx.com UG76S (v 13.4) January 18, 2012£ XILINX: Chapter 4: About Design Elements BUFGCTRL Primitive: Global Clock Control Buffer Introduction BUFGCTRL primitiveis a7 series global clock buffer that is designed as a synchronous/asynchronous "glitch free" 2:1 multiplexer with two clock inputs. Unlike simile global clock buffers, these clock buffers are designed ‘with more control pins to provide awider range of functionality and more robust input switching. BUFGCTRL. isnot limited to clocking applications, Port Descriptions Port Type Width Function ce Tnput (Clock enable input for the10 dock input A setup/held time must be guaranteed when you are using the CEO pin to enable this input Failure to meet thir requirement could rerult im a dock glitch Tapat (Clock enable input for thell dock input. A setup/held time must be guaranteed when you are using the CEI pin to enable this imput Fullure to meet this requirement could rerult ima dock glitch IGNORED Tnput ‘Clock ignore input for I mput. Asserting the IGNORE pin will ‘bypass the BUFGCTRL from detecting the conditions for switching between tivo lock inputs, In other words, ascerting IGNORE causes ‘the MUX to switch the inputs at the instant the select pin changes IGNOREO causes the output to switch away from the 10 input smmediately when the select pin changes, while IGNORE] causes ‘the output fo switch avoay from theTl input immediately when the select pin changes TGNOREI Tapat ‘Clock ignore input for mput. Asserting the IGNORE pin will ‘bypass the BUFGCTRL from detecting the conditions for switching between tivo lock inputs, In other words, ascerting IGNORE causes ‘the MUX to switch the inputs at the instant the select pin changes IGNOREO causes the output to switch away from the 10 input smmediately when the select pin changes, while IGNORE] causes ‘the output to switch avoay from theTIl input immediately when the select pin changes 10 Tapat Primary dock imput mto the BUFGCTRL enabled by the CEO input and selected by the 5D input, Tnput ‘Secondary dock input into the BUFGCTRL enabled by the CE] input and selected by the SI input Output Clock output Taput (Clock select input for 10. The Spins represent the dock select pin for each dock input. When using the Spin as input select, there is Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www xilinx.com atChapter 4: About Design Elements £ XILINX: Port Type [Width | Function a retup hold tine requirement Unlike CE pins failure to meat ar equirement wont rerult in a dock gitch. However, it an cause the tulput dock to appear one dogs ce later a Tape fT Clock select input for Il. The Spins represent the dock salea pin foreach dock mnput, When wsing the Spin as input seleg, theres a eup/hold tine requirement, Unlike CE pins laluretomeet thir Tequirement wont rerltn a dock glitch, However it an cause the tulput dock fo appear one dod cje ler Design Entry Method Tavantiation Recommended Tference Ne CORE Generator and wisards Ne Macro muppet Ne Available Attributes Allowed Attribute Type _| Values Detautt _ | Description INIT_OUT Deamal 0.1 3 Initializes the BUFGCTRL output tothe peaied value after configuration PRESLECT IO. [Boden [FALSE TRUE [FALSE | WTRUE BUFGCTRL oatpat aves input after confignation PRESLECT.H [Boden [FALSE TRUE [FALSE | WTRUE BUFGCTRL oatpat esl input after confignation Note Both PRESELECT attributes might not be TRUE at the same time VHDL Instantiation Template Unless they already exdst, copy the following two statements and paste them before the entity declaration. Xilinx 7 Series FPGA Libraries Guide for HDL Designs 82 wwwxilinx.com UG768 (v 13.4) January 18, 2012© XILINX. Chapter 4: About Design Elements Verilog instantiation Template J) surccrRit Global Clack Control suffer a 7 Serie 1) xsnine woe fez Guide, version 13.4 purccrat #1 750)» reitial value of eur (trance), // BOFGCTRE euzpue (TRALSE")" // BOFGCTRL eurpur 2 ouput (GVALUES?) O input’ (SYALUES)) 2 inpar (SUALUES)) J obits output: Clock output We oie Clock enable input for 10 We oie Eleck enable input for We oie Prinery clock We oie Secondary clock We oie Glock ignore input for 20 We oie Cleck igneee input fer 0150), We opie Glock selece for 20 S250) ests Elsck Select for hb 11 end of BUFGCTRLLinst inet For More Information See the 7 series FPGA User Documentation (User Guides ard Data Sheets). Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG76S (v 13.4) January 18, 2012 www xilinx.com 83Chapter 4: About Design Elements £ XILINX: BUFGMUX Primitive: Global Clock MUX Buffer iD Introduction BUFGMUX is amuiltipleced global clock buffer that can select between two input clocks: 10 and Il. When the select input (5) is Low, the signal on I is selected for output (0). When the select input (S) is High, the signal on Tis selected for output BUFGMUX and BUFGMUX_1 are distinguished by the state the output assumes when that output switches between clocks in response to a change in its select input. BUGFMUX assumes output state 0 and BUFGMUX_1 assumes output state 1 Note BUFGMUX guarantees that when Sis toggled, the state of the output remains in the inactive state until the nest active clock edge (either ID or Il) occurs. Logic Table Inputs Outputs 10 " s ° 0 x 0 0 x i 1 i x T 0 x L 0 Port Descriptions Port Type ‘Width Funotion 10 Input 7 Clos 0 input Hl Input 1 led input ° Output 1 Clock MUX output Input 1 Cloak select input Design Entry Method Tnetantiation Recommended Inference Ne (CORE Generator™ and wisards Ne Maco support Ne Xilinx 7 Series FPGA Libraries Guide for HDL Designs a4 wwwxilinx.com UG768 (v 13.4) January 18, 2012€ XILINX, Chapter 4: About Design Elements VHDL Instantiation Template Unless they already exdst, copy the following two statements and paste them before the entity declaration. Verilog Instantiation Template J) surcitx: Global clock sux & a 7 1) xsnine aoe 1) end of BUFGHHK inst instantiation For More Information See the 7 series FPGA User Documentation (User Guides aud Data Sheets) Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG76S (v 13.4) January 18, 2012Chapter 4: About Design Elements £ XILINX: BUFGMUX_1 Primitive: Global Clock MUX Buffer with Output State 1 By Introduction ‘This design dement is amultiplexed global clock buffer that can select between two input clocks: 10 and Il ‘When the select input (S) is Low, the signal on Il is selected for output (0). When the select input (S) is High, the signal on Il is selected for output. ‘This design clementis distinguished from BUFGMUX by the state the output assumes when that output switches between clocksin response to a change in its select input. BUFGMUX assumes output state0 and BUFGMUX_1 assumes output state 1 Logic Table Inputs Outputs 10 " s ° 0 x 0 0 x i 1 i x T 1 x J 1 Design Entry Method Tnetantiation Yer Tnference Recommended (CORE Generator™ and wisards Ne Maco support Ne VHDL Instantiation Template Unless they already exdst, copy the following two statements and paste them before the entity declaration. Xilinx 7 Series FPGA Libraries Guide for HDL Designs 86 wwwxilinx.com UG768 (v 13.4) January 18, 2012€ XILINX, Chapter 4: About Design Elements Verilog Instantiation Template For More Information See the 7 series FPGA User Documentation (User Guides aud Data Sheets) Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG76S (v 13.4) January 18, 2012 www. inx.com 87Chapter 4: About Design Elements £ XILINX: BUFGMUX_CTRL Primitive: 2-to-1 Global Clock MUX Buffer Introduction ‘This design elementiis a global lock buffer with two dock inputs, one dock output, and a select line used to cleanly select between one of two clocks driving the global clocking resource. This component is based on BUFGCTRL, with some pins connected to logic High or Low. This element uses the S pin as the select pin for the 2+to-l MUX $ can switch anytime without causing a glitch on the output clock of the buffer Port Descriptions Port Direction Width Function ° Output bit Clock Output 10 Input 1 bit (One of two Clodk Inputs Input bit (One of two Clock Inputs 3 Input bit Select for 10 (S=0) or 11 (1) Clock Output Design Entry Method Tnvantiation Yer Tnference Recommended CORE Gemerater™ and winards Ne ‘Macro support Ne VHDL Instantiation Template Unless they already exdst, copy the following two statements and paste them before the entity declaration. Xilinx 7 Series FPGA Libraries Guide for HDL Designs 8 wwwxilinx.com UG768 (v 13.4) January 18, 2012€ XILINX, Chapter 4: About Design Elements Verilog Instantiation Template BUFCMRXLCTRE BUFGHUX CTRILinst ( For More Information See the 7 series FPGA User Documentation (User Guides aud Data Sheets) Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG76S (v 13.4) January 18, 2012 www xilinx.com 89Chapter 4: About Design Elements £ XILINX: BUFH Primitive: HROW Clock Buffer for a Single Clocking Region eur St Oo} Introduction ‘The BUFH primitive allows direct access to the clock region entry point of the global buffer BUFG) resource This allows access to unused portions of the global clocking network to be used as high-speed, low skew local (single clock region) routing resources, Please refer to the/’ series FPGA Clocking Resources User Guide for details for using this component. Port Descriptions Port Type Width Function 1 Input 1 Clock input ° Output 1 Clock output Design Entry Method Tnetantiation Yer Tnference Ne (CORE Generator™ and wisards Ne Maco support Ne For More Information See the 7 series FPGA User Documentation (User Guides aud Data Sheets) Xilinx 7 Series FPGA Libraries Guide for HDL Designs 90 wwwxilinx.com UG768 (v 13.4) January 18, 2012€ XILINX. Chapter 4: About Design Elements BUFHCE Primitive: HROW Clock Buffer for a Single Clocking Region with Clock Enable BUFHCE ce Co) Introduction ‘The BUFHCE primitive allows direct access to the clock region entry point of the global buffer BUFG) resource This allows access to unused portions of the global clocking network to be used as high-speed, low skew local (single clock region) routing resources. Addtionaly, the CE or clock enable input allows for fimer-grained control of clock enabling or gating to allow for power reduction for circuitry or portions of the design not constantly used. Please refer to the7 series FPGA Clocking Resources User Guide for details for using this component. Port Descriptions Port Type Width | Function cE Input 1 Enables propagation of signal from Ito 0. When low, performs a ghtchless transition of the output fo INIT_OUT value, 1 Input 1 Clock input ° Output 1 Clock output Design Entry Method Tnetantiation Yer Tnference Ne (CORE Generator™ and wisards Ne Maco support Ne Available Attributes Attribute Type Allowed Values | Default | Description CELTWPE STRING — | "SYNC", "ASYNC™| SYNC” | Sets dock enable behavicr where "SYNC" allows for a gitchless transition to and from the INIT_OUT Nalue, "ASYNC"is generally used to create a more immediate transition such ar when you can expec the dock to be stopped or when using the BUFHICE. for ahigh fanout control or data path routing instead of a dock buster. INIT_OUT DECIMAL [0,1 0 Initial output value, aleoidicates top low vs top high behavior Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www xilinx.com aChapter 4: About Design Elements € XILINX. VHDL Instantiation Template Unless they already exist, copy the following two statements and paste them before the entity declaration. Verilog Instantiation Template 1) surwce: now ch with clock gnable a 7 1) xsnine woe net), // emit (gitichte: immediate switch (i tnitial outpet 1) end of BUPHCE inst instantiation For More Information See the 7 series FPGA User Documentation (User Guides aud Data Sheets) Xilinx 7 Series FPGA Libraries Guide for HDL Designs 92 wwwxilinx.com UG76S (v 13.4) January 18, 2012€ XILINX. Chapter 4: About Design Elements BUFIO Primitive: Local Clock Buffer for /O. Introduction ‘This design elementis simply a dock-in, clock-out buffer It drives a dedicated clock net within the I/O column, independent of the global clock resources. Thus, these elements are ideally suited for source-synchronous data capture (forwarded/receiver dock distribution). They can be driven by a dedicated MRCC I/O located in the same clock region or aBUFMRCE/BUFMR component capable of clocking multiple clock regions. The BUFIO can only drive I/O components within the bank in which they exist. These elements cannot directly drive logic resources (CLB, block RAM, etc) because the I/O clock network only reaches the I/O column Port Descriptions Port Type Width Function 1 Input 1 Input part to dock buifer. Connect this to an IBUFG connected to a top-level port of an asroaated BUFR buffer. ° Output 1 (Output port from dock buffer Connect this to the dock inputs to synchronous 11/0 components like the ISERDESE?, OSERDESE2, IDDR, ODDR or register connected directly toan I/O port (inferred or instantiated) Design Entry Method Tnetantiation Yer Tnference Ne (CORE Generator™ and wisards Ne Maco support Ne VHDL Instantiation Template Unless they already exdst, copy the following two statements and paste them before the entity declaration. Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www xilinx.com 93Chapter 4: About Design Elements £ XILINX. Verilog Instantiation Template For More Information See the 7 series FPGA User Documentation (User Guides aud Data Sheets) Xilinx 7 Series FPGA Libraries Guide for HDL Designs 94 wwwxilinx.com UG76S (v 13.4) January 18, 2012€ XILINX. Chapter 4: About Design Elements BUFMR Primitive: Multi-Region Clock Buffer eUEMA Introduction ‘The BUFMR is a simple clock-in/clock-out buffer The BUFMR replaces the multi-region/bank support of the BUFR and BUFIO available in prior Virtex architectures. There aretwo BUFMRsin every bank, and each buffer can be driven by one specific MRCC in the same bank. The BUFMRs drive the BUFIOs and/or BUFRs in the same region/banks and in the region above and below viathe I/O clocking backbone. It is not suggested to use a BUFMR when driving BUFRs using dock dividers (not in bypass) and instead use aBUFMRCE component. Port Descriptions Port Type Width | Function T Tnpat 7 BUFMR dock input pin, Connect toan IBUFG input that in tum i+, directly connected toa MRC 1/0 pert ° Output 1 BUFMR dock output pin. Connect to BUFIOs and/or BUFRs to be driven in the same and adjacent regions Design Entry Method Tnetantiation Yer Tnference Ne (CORE Generator™ and wisards Ne Maco support Ne VHDL Instantiation Template Unless they already exdst, copy the following two statements and paste them before the entity declaration. Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www. inx.com 95Chapter 4: About Design Elements £ XILINX. Verilog Instantiation Template For More Information See the 7 series FPGA User Documentation (User Guides aud Data Sheets) Xilinx 7 Series FPGA Libraries Guide for HDL Designs 96 wwwxilinx.com UG76S (v 13.4) January 18, 2012€ XILINX. Chapter 4: About Design Elements BUFMRCE Primitive: Multi-Region Clock Buffer with Clock Enable BORIACE Introduction ‘The BUFMRCE is a simple clock-in/dock-out buffer with clock with clock enable (CE), Asserting CE stops the output clock to auser specified value The BUFMRCE replaces the multi-region/bank support of the BUFR and BUFIO available in prior Virtex architectures. There are two BUFMRCEs in every bank and each buffer can be driven by one specific MRC in the same bank. The BUFMRCE drives the BUFIOs and/or BUFRs in the same region/banks and in the region above and below via the I/O clocking backbone When using BUFR dividers (not in bypass), the BUFMICE must be disabled by deasserting the CE pin, the BUFR must be reset (cleared by asserting CLR), and then the CE signal should be asserted. This sequence ensures that all BUFR output clocks are phase aligned. Ifthe dividers within the BUFRs arenot used, then this additional circuitry isnot necessary. Ifthe clock enable circuitry is not needed, aBUFMR component should be used in place of aBUFMRCE Port Descriptions Port Type Width | Function Tnput 1 ‘Active high buffer enable mput, When low, output will stile to INIT_OUT value. 1 Tnput 1 BUFMR dock input pin, Connect to an IBUFG input that in tum i= directly connected toa MRC 1/0 pert ° Output 1 BUFMR dock output pin. Connect to BUFIOs and/or BUFRs to be driven in the same and adjacent regions Design Entry Method Tnvantiation Yer Tnference Ne CORE Gemerater™ and winards Ne ‘Macro support Ne Available Attributes Attribute Type Allowed Values _| Default Description CELTWPE ‘Sang. ‘SYNC, "ASYNC ‘SYNC! Set to “SYNC "for CE to be synchronous toinput land create a glitchlers oatput Set to "ASYINC for stopped dock or non-dock operation of the CE signal. INIT_OUT Deamal [01 0 Initial output value, alsoindicates stop low vs stop high behavior Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www xilinx.com 7Chapter 4: About Design Elements € XILINX. VHDL Instantiation Template Unless they already exist, copy the following two statements and paste them before the entity declaration. Verilog Instantiation Template 1) surunce: suiti-Region clock a 7 1) xsnine aoe Guide, version 13.4 mem), #7 snc, ASYM Y) inivial output and stepped polarity, (0-1) 1) end of BUFERCE inst instantiation For More Information See the 7 series FPGA User Documentation (User Guides aud Data Sheets) Xilinx 7 Series FPGA Libraries Guide for HDL Designs 98 wwwxilinx.com UG76S (v 13.4) January 18, 2012€ XILINX. Chapter 4: About Design Elements BUFR Primitive: Regional Clock Buffer for /O and Logic Resources within a Clock Region Introduction ‘TheBUFR is aregional dock buffer available in series devices. BUFRs drive clock signals to a dedicated clock net within a dock region, independent from the global clock tree. Each BUFR can drive the regional clock netsin the region in which itis located. Unlike BUFIOs, BUFRs can drive the I/O logic and logic resources (CLB, block RAM, etc) in the esting dock region. BUFRs can be driven by atther the output from an IBUFG, BUFMRCE, MMCM orlocal interconnect. In addition, BUFRs are capable of generating divided clock outputs with respect to the clock input. The divide value is an integer between one and eight. BUFRs are ideal for source-synchronous applications requiring clock domain crossing or serial-to-parallel conversion. There are two BUFRs in atypical clock region (two regional clock networks). local clocking is needed in multiple clock regions, the BUFMRCE can drive multiple BUFRs in adjacent clock regions to further extend this clocking capability. Please refer to the BUFMRCE for more details Port Descriptions Port Type Width | Function cE Tapat 1 ‘Clock enable port. When arserted Low, this port disables the output lock at port ©. When asserted High, this port resets the counter used to produce the divided dock output Connect to gnd when BUFR_DIVIDE is set to "BYPASS" cue Input 1 ‘Counter reset for divided dock output. When asserted high, this port resets the counter ured toproduce the divided dock output’ Connect 40 GND when BUFR_DIVIDE is set to BYPASS" 1 Input 1 ‘Clodk input port, This port i the dock source port for BUFR. Tt can bbe driven by an IBUFG, BUFMRCE, MMCM or local interconnect. ° Output 1 ‘Clock output port. This part driver the dock tradks in the dock region of the BUFR. This port connects toFPGA docked components Design Entry Method Tnetantiation Yer Inference Ne (CORE Generator™ and wicards Yer Maco support Ne Available Attributes Attribute Type _| Allowed_Values Default Description BUFRDIVIDE | Sting | BYPASS, 12,3, | ‘BYPASS! ‘Defines whether the output dock ira 4°", "6", 75,8 divided version of input dock SMDEVICE | Suing | 7SERIES, VIRTEXG, | ‘7SERIES For correct amulation behavior, this “VIRTEXS', "VIRTEX6' attubute must be set to SERIES’ when targeting a7 series device Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www. inx.com 99Chapter 4: About Design Elements € XILINX. VHDL Instantiation Template Unless they already exist, copy the following two statements and paste them before the entity declaration. Generic map ion Template J BurR: Regional Clock Buffer for 1/0 and Logic Resources within 2 Clock Region a 1 Sense 1) xsnine aoe BUFR #1 BUFRDIVIDE("BYPASS"), // Values: "BYPASS, 1, 2, 3, 4 Sy 81 Te BY SEMLDEVICE (TTSERIES") | // Mort be aet ro. "7SERZES* J) end of BUFR inst instantiation For More Information See the 7 series FPGA User Documentation (User Guides ard Data Sheets). Xilinx 7 Series FPGA Libraries Guide for HDL Designs 100 wwwxilinx.com UG76S (v 13.4) January 18, 2012€ XILINX. Chapter 4: About Design Elements CAPTUREE2 Primitive: Register Capture ‘CAPTOREES Introduction ‘This clement provides user control and synchronization over when and how the capture register (flip-flop and latch) information task is requested. The readback function is provided through dedicated configuration port instructions. However, without this element, the readback datais synchronized to the configuration clock. Only register (Hip-flop and latch) states can be captured. Although LUT RAM, SRL, and block RAM states are readback, they cannot be captured. An asserted high CAP signal indicates that the registers in the device are to be captured at thenext Low-te-High clock transition By default, datais captured after every trigger when transition on CLK while CAP is asserted. To limit the readback operation to a single data capture, add the ONESHOT-TRUE attribute to this element. Port Descriptions Port Type Width | Function CAP, Tnput 1 Capture Input cK Tapat 1 Clock Input Design Entry Method Tnetantiation Recommended Tnference Ne (CORE Generator™ and wisards Ne Maco support Ne Available Attributes Attribute Type Allowed Values __| Default Description ONESHOT Sing. TRUE, FALSE TRUE Species the procedure for performing single readback per CAP tigger Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www. inx.com 101Chapter 4: About Design Elements € XILINX. VHDL Instantiation Template Unless they already exist, copy the following two statements and paste them before the entity declaration. Verilog Instantiation Template 1) caprunee2: capture a au U1 endo For More Information See the 7 series FPGA User Documentation (User Guides aud Data Sheets) Xilinx 7 Series FPGA Libraries Guide for HDL Designs 402 wwwxilinx.com UG76S (v 13.4) January 18, 2012€ XILINX. Chapter 4: About Design Elements CARRY4 Primitive: Fast Carry Logic with Look Ahead Introduction ‘This circuit design represents the fast cay logic for aslice. The carry chain consists of a series of four MUXes and four XORs that connect to the other logic (LUTs) in the slice via dedicated routes to form more complex functions, The fast carry logic is useful for building arithmetic functions like adders, counters, subtractors and add/subs, as well as such other logic functions as wide comparators, address decoders, and some logic gates (specifically, AND and OR) Port Descriptions Port Direction Width | Function ° Output a Cany chain KOR general data out co. Ontpat a Cony out of each stage of the ary Guin Dr Tnpet 3 Cony MUX data input 3 Tnpat a Cany MUX seed line cunt lye 7 Conyin intindation input a Tnpat 7 Cany aveadeinput in Entry Method Tavantiation Yer Trference Recommended CORE Generator and wisards Ne Maco sppat Ne Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www. inx.com 103Chapter 4: About Design Elements € XILINX. VHDL Instantiation Template Unless they already exist, copy the following two statements and paste them before the entity declaration. Verilog Instantiation Template 1) cannes Fase a 7 1) xsnine woe : Up tobis carey o We Obit carey el : Yo bie carey © nen), // Lobie carey ini BE IDE), Wo (obit cersy-MOx data in S13) () (bie Seery-Mox selec input 1) end of CARRE inst instantiation For More Information See the 7 series FPGA User Documentation (User Guides aud Data Sheets) Xilinx 7 Series FPGA Libraries Guide for HDL Designs 104 wwwxilinx.com UG76S (v 13.4) January 18, 2012€ XILINX. Chapter 4: About Design Elements CFGLUTS Primitive: 5-input Dynamically Reconfigurable Look-Up Table (LUT) “crane Introduction ‘This clement is aruntime dynamically reconfigurable, 5-input look-up table (LUT) that enables the changing of the logical function of the LUT during circuit operation. Using the CDI pin, anew INIT value can be synchronously shifted in serially to change the logical function. The O6 output pin produces the logical output function, based on the current INIT value loaded into the LUT and the currently selected 10-Id input pins Optionally, you can use the 5 output in combination with the 06 output to create two individual 4-input functions sharing the same inputs or a5-input function and a4-input function that uses a subset of the 5-input logic (see tables below). This component occupies one of the four 6-LUT components within a slice To cascade this element, connect the CDO pin from each element to the CDI input of the next element. This will allow asingle serial chain of data (32-bits per LUT) to reconfigure multiple LUTs, Port Descriptions Port Direction | Width | Function G3 Outpat | T SLUT output Gg Outpat [1 “ELUT output 101,256 | Input 1 LUT impute Do Outpat [1 Reconfiguration data cascaded output (optionally connect to the CDIimput of a subsequent LUT) I Tapat 1 Reconfiguration data serial mput cK Tapat 1 Reconfiguration dock oS Tapat 1 ‘Active high reconfiguration dock enable Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www xilinx.com 105Chapter 4: About Design Elements £ XILINX: Design Entry Method Tnetantiation Recommended Inference Ne (CORE Generator™ and wisards Ne Maco support Ne + Connect the CLK input to the clock source used to supply the reconfiguration data + Connect the CDI input to the source of the reconfiguration data + Connect the CE pin to the active high logic if you need to enable/disable LUT reconfiguration. + Connect the ID pins to the source inputs to the logic equation. The logic function is output on 06 and O5 + To cascade this element, connect the CDO pin from each element to the CDI input of thenext element to allow a single serial chain of datato reconfigure multiple LUTs, ‘The INIT attribute should be placed on this design element to specify the initial logical function of the LUT. A new INIT ca beloaded into the LUT any time during circuit operation by shifting in 32-bits per LUT in the chain, representing the new INIT value. Disregard the 06 and 05 output data until all 32-bits of new INIT data has been docked into the LUT. The logical function of the LUT changes as new INIT datais shifted into it. Data should be shifted in MSB (INIT[31}) first and LSB (INIT(O}) last. In order to understand the 06 and O5 logical value based on the current INIT, see the table below. 1413121110 (06 Value (05 Value i INITSI] INTIS] 11110 INTO) INIT] 10001 INIT INITHY 10000 INITHG) INITIO) o1lit INITS] INTIS o1ii9 INIT] INIT] 00001 INIT INITHY 00000 INITIO) INITIO Forinstance, the INIT value of FFFF8000 would represent the following logical equations © 06+ Mor(B and 2 andl and 0) + 05=Band2 andl dD Touse these elements as tivo, 4-input LUTS with the same inputs but different functions, tie the Hl signal to a logical one. The INIT[31 16] values apply to the logical values of the 06 output and INIT [150] apply to the logical values of the O5 output. Available Attributes Attribute [Type Allowed Values Default _| Description INIT Hexadeamal | Any 32-bit Value ‘Allzeros | Species the initial logial expression of this element Xilinx 7 Series FPGA Libraries Guide for HDL Designs 106 wwwxilinx.com UG768 (v 13.4) January 18, 2012© XILINX. Chapter 4: About Design Elements VHDL Instantiation Template Unless they already exist, copy the following two statements and paste them before the entity declaration. <- crauurs: Reconfigurable S-input LUT (lapped to SiiceM 2Ur6) opt "e700000000") ion Template J) crauur5: Reconfigurable S-input LUT (Mapped to a Siiceit LOTS) a Tse: 1) xsnine aoe crawrs +1 2427 (32"h00000000) // Specify initial UT contents B0UZ0), | // Lagi nua}, // uagie p02), // bogie Btn), // nagie 2408) regi hb 1) ena of c¥ouuTS_inst For More Information See the 7 series FPGA User Documentation (User Guides ard Data Sheets). Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG76S (v 13.4) January 18, 2012 www xilinx.com 107Chapter 4: About Design Elements £ XILINX: DCIRESET Primitive: Digitally Controlled Impedance Reset Component Introduction ‘This design elements used to reset theDigtlly Controlled impedance (DCI) state machine after configuration hhas been completed. By toggling the RST input fo the DCIRESET primitive while the devices operating theDCI satemachine i reset and both phases of impedance adjustment proceed in succession All Ys using DCI will bbetnavalable unt the LOCKED output from the DCIRESET bloc is asserted Port Descriptions Port Type Width _| Function LOCKED Output 1 DCI satemachine LOCK status output ‘When low, DCII/O impedance is being calibrated and DCI 1/Os are unavailable Upon a lov-te-high assertion, DCI/Os are available for wee RST Input 1 ‘Asive high aryachronoas reset imput to DCI statemachine. After RST is azserted, 1/0s wbiizing DCI wall be unavailable until LOCKED is asserted, Design Entry Method Tnvantiation Yer Tnference Ne CORE Generator and wisards Ne Maco support Ne VHDL Instantiation Template Unless they already exdst, copy the following two statements and paste them before the entity declaration. Xilinx 7 Series FPGA Libraries Guide for HDL Designs 108 wwwxilinx.com UG768 (v 13.4) January 18, 2012£ XILINX. Verilog Instantiation Template For More Information See the 7 series FPGA User Documentation (User Guides aud Data Sheets) Chapter 4: About Design Elements Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG76S (v 13.4) January 18, 2012 www xilinx.com 109Chapter 4: About Design Elements £ XILINX: DNA_PORT Primitive: Device DNA Access Port ONA_PORT —— on cour |} ——] revo ——] sur Introduction ‘The DNA PORT ellows access to a dedicated shift register that can be loaded with the Device DNA databits (actory-programmed, read-only unique ID) for a given? series device. In addition to shifting out the DNA data bits, this component allows for the inclusion of supplemental bits of your data or allows for the DNA data to rollover (repeat DNA data after initial datahas been shifted out). This component is primarily used in conjunction with other dreuiby to build added copy protection for the FPGA bitstream fram possible theft. Connect all inputs and outputs to the design to ensure proper operation To access the Device DNA data you must frst load the shift register by setting the active high READ signal for one clock cycle After the shuft register isloaded, the data can be synchronously shifted out by enabling the active high SHIFT input and capturing the data out theDOUT output port. Additional data can be appended to the end of the 57-bit shift register by connecting the appropriate logic to the DIN port. If DNA data rollover is desired, connect the DOUT part directly to the DIN port to allow for the same datato be shifted out after completing the 57-bit shift operation. If no additional datais necessary, the DIN port can be tied to alogic zero. The attribute SIM DNA, VALUE can be optionaly set to allow for simulation of apossible DNA data sequence. By default, theDevice DNA data bits are all zeros in the strmulation model Port Descriptions Port Type Width Function cK apt Clock input DIN’ Input User data input pin Dour Output DNA output data READ Input ‘Active high load DNA, active low read input FT Input ‘Active high aft enable input Design Entry Method Tnetantiation Recommended Inference Ne (CORE Generator™ and wisards Ne Maco support Ne Xilinx 7 Series FPGA Libraries Guide for HDL Designs 110 wwwxilinx.com UG768 (v 13.4) January 18, 2012€ XILINX, Chapter 4: About Design Elements Available Attributes Attribute Type _| Allowed Values _| Default Description SMDNA_VALUE | Hex ‘57730000000 all zeros Species a sample 57-bit DNA value for (00000000 +0 simulation By Lene Ed VHDL Instantiation Template Unless they already exdst, copy the following two statements and paste them before the entity declaration. Verilog Instantiation Template For More Information See the 7 series FPGA User Documentation (User Guides aud Data Sheets) Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG76S (v 13.4) January 18, 2012 atChapter 4: About Design Elements £ XILINX. DSP48E1 Primitive: 48-bit Multi-Functional Arithmetic Block pseaset [acnves.) JaLuwo0e(s0) 22.0) eciw79) pez) cour('70) mmm canrinsELi0) lier.) pr240) caanvours0) fmm rane) loPmooete) Poim7.0) —ennevcason Peour70) mmm errs —ceas —foenz wr) —cero —|ceaumooe —ces —cesz cannycascour} — —eec —eecannvn —eecra utrsignour} — —ceo —cenmove —eew —cer —fax — aversion —rsta partenNeperect}— —rstaucannvn —rstarumooe —rste —rste —rsterr. —frsto —rstinwooe unperrLow|— —rsm —rste overrtow}— Partennoerect} — Introduction This design dlementis aversaile, scalable, hard IP block within? series devices that allows for the creation of compact, high-speed, arthmetic:intensive operations, such as those seen for many DSP algonithims. Some of the Runctions capable within the block include multiplication, addition, subtraction, accumulation, shifting, logical operations and pattern detection. Xilinx 7 Series FPGA Libraries Guide for HDL Designs 112 wwwxilinx.com UG768 (v 13.4) January 18, 2012£ XILINX: Chapter 4: About Design Elements ‘When dataports A,B, C, and D arenot used, and to reduce leakage power dissipation, the dataport input signals must be tied High, the port input register must be selected, and the CE and RST input control signals must betied Low. An example of unused C port recommended settings would be: C[47:0]= all ones, CREG CEC=0, and RSTC All signals ave activeHigh, Port Desc! ions Port Type Width Function De Tnput Data input for preadder, multiplier, adder/subtracter/accumulater, ALU or concatenation operations. When used with the multiplier or preadder, 25 bite of data (A[240)) is used and upper bits (A[29.25)) Are unused and maybe tied to ground. When weing the internal adder/subctracter/accumulater or ALU drcuit, all 30 bits are used (A290). When used in concatenation mode, all 30 bits areused and this constitutes the MSB (app et bit ofthe concatenated vector "ACING290> Input Cascaded data input from ACOUT of previous DSPABEL alice (Guuxed wth A) Lenot used, tie port to all zeros, This signal isa dedicated routing path internal to the DSPAGE] column. Its not ccersible wa fabric routing resources ‘ACOUTE290> Output Cascaded data output to ACIN of next DSPASEI alice. not used, leave unconnected. This signal isa dedicated routing path intemal to the DSPASEI column, It ie not accessible via fabricreuting resources “ALUMODEG.> Input Controls the selection of the logic function in the DSP ABEL slice Baro Tnput 18 ‘The B input of the multiplier B[I7.0] are the least significant bite (LSB:) ofthe AB concatenated input to the second-stage. adder/subtracter or logic function. BCINAITO> Input 18 Cascaded data input from BCOUT of previous DSPASEI slice (qauxed with B). not used, te port toall zeros. This signal ie dedicated routing path internal to the DSPASEI column. Its not accessible wa fabric routing resources BCOUTATO> Output 1 Cascaded data output toBCIN of next DSPISEI alice Ifnot weed, leave unconnected. This signal is a dedicated routing path internal to the DSPASEI column, It ie not accessible va fabricreuting resources Calra> Taput Data input tothe second-stage adder/subtracter pattem detector, or Togic function ‘CARRYCASCIN Input Cascaded carry input froin CARRY CASCOUT of previous DSPASEL slice. This signalis a dedicated routing path internal tothe DSPGE] column, tis not accezable via fabric routing resources ‘CARRYCASCOUT Output Cascaded carry output fo CARRYCASCIN of next DSPISEL clice ‘This signal is internally fed back intothe CARRYINSEL multiplexer anput of the same DSPISE] slice, This Taput [3 Seeds the carry source: + 011-PCIN[s7]- Rounding PCIN (round towards zero) + 100. CARRYCASCOUT- Fer larger ada/sub/ace (sequential operation via internal feedback). Must select with PREG+1 + 101. ~P[47]- Rounding P (round toveards infinity). Must select with PREGeL © 110-A(24]-XNOR BIL7] Rounding AxB + 111. P[s7]- ForroundingP (round towards zero). Mast select with PREG=I CARRYOUTS: © Outpar [a “bit carry output from each 12 bitfield oftheaccumulate/adderlogic wunit, Normal 48-bit op eration uses only CARRYOUTS. SMD operation can tse four carry out bits (CARRYOUTIS 0), ‘CEAD Input [1 “Active high, dock enable for the pre adder output AD pipeline register. Tie to logic one if not used and ADREG1. Tie to logic zero if ADREG0. ‘CEALUMODE Input [1 ‘Active High, dock enable for ALUMODE (contral inputs) registers (ALUMODEREG=1), Tie tologic onesf not used. CEAL Input [1 ‘Active high, dock enable forthe frst A (put) register This port s+ only used sf AREG=2 or INMODED=1. Tis tologic oneifnot used and AREG=2. The to logic zeroif AREG-0 or 1. When two registers fare used, this is the rst sequentially. When Dynamic AB Access ie used, this dock enable is applied for INMODE(01 CEAD Input [1 “Active high, dock enable forthe second A (put) register, This port is onlyused sf AREGI or 2. Tie tologic onesfnot used and AREG1 or 2 Tietologiczero if AREG-0. When two registers are used, this 4s the second sequentially. When one register is used (AREG=1), CEA2 is the dock enable CERI Input [1 ‘Active high, Clock enable for the first B (put) register. This port is only used sf BREG=2 or INMODEM=I. Tie to logic ane if not used and BREG=2. Tie to logic zero f BREGO or 1. When two registers reused, this is the Srst sequentially. When Dynamic AB Access ie uused, this dock enable is applied for INMODE(4I1 (CEB Input [1 “Active high, dock enable for the second B (input) register. This pow i onlyused if BREG+] or 2. The tologic oneif not ured and BREG=1 or2 Tietologiczerosf BREG-0. When tworegisters are used, thie is the second sequentially, When one register isused (BREG+1), CEB2 is the dock enable. CEC Input [1 ‘Active High, Clock enable for the C input) register (CREG=1). The tologic one if not used. ‘CECARRYIN Taput [7 ‘Active high, dock enable for the CARRYIN (imput from fabrio) register (CARRYINREG1). Tie tologic one if not weed CECTRE, Input [1 ‘Active high, dock enable for the OPMODE and CARRYINSEL (control inputs) registers (OPMODEREG&1 or CARRYINSELREG+1), The tologic ane sf not weed. cD Taput [7 “Active high, Clock enable for the D (aaput) registers DREG=I), Tie tologic one if not used. ‘CEINMODE, Input [1 “Active high, dock enable for the INMODE contral input registers GNMODEREG1), Te to logic one ifnot used cM Input [1 “Active high, Clock enable for the post multiply M (pipeline) register and the intemal multiply round CARRYIN register (MREG+1). Tie to logic one if not used. Xilinx 7 Series FPGA Libraries Guide for HDL Designs 114 wwwxilinx.com UG768 (v 13.4) January 18, 2012£ XILINX: Chapter 4: About Design Elements Type Width Function Taput ‘Active high, dock enable for the P (output) register PREG). Tie tologic one if not used. Input “This port ithe DSPUSE] input dock, common toall internal registers and fip-dlops Dawe Input 26-bit data mput to the pre-adder or altemative input to the multiplier. The preadder implements D+ Aas determined by the INMODES signal. INMODECAG> Input “There five control bite select the functionality of the pre-adder the ALB. and D inputs, and the input registers. These bits should be tied toall zeroes if not weed, ‘MULTSIGNIN Input ‘Sign of the multiplied rerult fom the previous DSPIGEI slice for MAC extension. Esther connect tothe MULTSIGNOUT of another DSP block of tie to ground sf not used. This agnalis a dedicated routing path intemal to the DSPASEI column. Itisnot accersble via fabric Fouting resources MULTSIGNOUT Output Sign of the multiplied rerult cascaded to the nect DSPABEl slice for MAC extension. Esther connect to the MULTSIGNIN of another DSP block or tie to ground sf not used. This signal isa dedicated routing path intemal to the DSPASEI column. Itisnot accersble via fabric Fouting resources OPMODESO> Input Controls the mput tothe X,Y, and Zmultiplecers in the DSPASEL slice dictating the operation or function of the DSP slice OVERFLOW Output ‘Active high Overdlow indicator when used with the appropriate setting ofthe pattem detector and PREGL Palro> Output Data output from second stage adder/subtracter ox logic function. PATTERNEDETECT Output “Active high match indicator between PIA7 O]and the patter bar PATTERNDETE CT Output “Active high Match indicator betvween P[S7.0] and the pattern gated bythe MASK Result amives on the same cycle as P. PCINATO> Input Cascaded data imput from PCOUT of previous DSPUSEI slice to adder Ifused, connect toPCOUT of upstream cazcaded DSP slice Ifnot weed, tie port to all zeros. This signal isa dedicated routing path internal to the DSPASEI column. It ie not accessible va fabric Fouting resources. PCOUTEATO> Output Cascaded data output to PCIN of next DSPASEI alice, Ifused, connect to PCIN of downstream cascaded DSP slice. If not used, leave unconnected. This signal is a dedicated routing path intemal to the DSPASEI column, It ie not accessible via fabricreuting resources STA, Input ‘Active high, synchronous Reset for both A (put) registers (AREGI or 2). Thetologic zero ifnot weed RSTALLCARRY IN Input “Active high, synchronous reret for the Carry (internal path) and the CARRYIN registers (CARRYINREG+1), Tee to logiczerosfnot weed RSTALUMODE Input ‘Active high, syadwonous Reset for ALUMODE (control impute) registers (ALUMODEREG+1). Tie tologic zero f not used. RST Input ‘Active high, synchronous Reset for both B Gmput) registers (BREGHI or 2). Tieto logic eroifnot weed RSTC Taput “Active high, synchronous reset for the C Gaput) registers (CREG-I) The tologic zero if not used RSTCTRL Input ‘Active High, synchronous reset for OPMODE and CARRYINEEL (control inputs) registers (OPMODEREG*1 and/or CARRYINSELREG+1). Tieto logiezeroif not used Xilinx 7 Series FPGA Libr jes Guide for HDL Designs UG768 (v 13.4) January 18, 2012 www xilinx.com 115Chapter 4: About Design Elements £ XILINX: Port Type [Width | Function RSD Taput [1 ‘Active high, synchronous reset for the D (aput) register and for the pre-adder (output) AD pipeline register (DREGI and/or ADREG1), Tie tologiezeroit not used RSTINMODE Input [1 “Active high, synchronous reset for the INMODE (control mput) registers (NMODEREG+1), Tie to logiczeroif not used RSM Taput [7 “Active high, synchronous reset for the M (pipeline) regiters QUREG=I) Te tologiczeroif not used RSP Input [1 ‘Active high, synchronous reset for theP (output) registers PREG). The to logic zero f not used UNDERFLOW Outpae [2 ‘Active high wnderdow indicator when used with the appropriate setting ofthe pattem detector and PREG=L Design Entry Method Tnstantiation Yer Inference Recommended (CORE Generator™ and wicards Yes Maco support Yer Available Attributes Attribute Type ‘Allowed Values | Default Description ‘AINPUT ‘Sting, "DIRECT DIRECT Selects the iput to the A port between parallel ‘CASCADE! input (DIRECT) or the cavcaded input from the previous slice ("CASCADE") "ACASCREG Deamal [1,02 7 Tn conjunction with AREG, celects thenumber of ‘Aunput registers on the A cascade path, ACOUT. ‘This attaibute must be equal to or ane less than the AREG value © AREG-O: ACASCREG must be 0 © REG: ACASCREGmust bel + AAREG-2: ACASCREG can bel 2 “ADREG Deamal [1,0 1 Selects the number of AD pipeline registers. Set tol touse the AD pipeline registers, ALUMODEREG [Deamal [1,0 1 Selects the number of ALUMODE input registers: Set to toregister the ALUMODE snputs “AREG Deamal [1,02 1 Selects the number of Amput pip dime registers AUTORESET | Suing "NO_RESET NORESET’ | Automatically reretstheP Register (accumulated “PATDET "RESET MATCH ‘value or counter value) on the next dock "RESETNOT_ tye, if patter detect event has occurred on. MATCH this dock cycle. The RESET MATCH” and "RESET NOT MATCH” settinge distinguish between whether the DSPABEI slice should cause an autoreset of the P Register on the next cycle: Tif the pattern is matched or - whenever the pattem isnot matched on the current cyde but as matched on the previous dock eyde, Xilinx 7 Series FPGA Libraries Guide for HDL Designs 116 wwwxilinx.com UG768 (v 13.4) January 18, 2012£ XILINX: Chapter 4: About Design Elements Attribute Type Allowed Values | Default Description BINPUT Sing "DIRECT! DIRECT Selects the input tothe B p ort between parallel ‘CASCADE! input (DIRECT) or the cascaded input from the previous slice ("CASCADE") 'BCASCREG Deammal [1,02 1 Tn conjunction with BREG, selects the number of Banput registers on the B cascade path, BCOUT. ‘This attibute must be equal to or one less than the BREG value © BREG0: BCASCREG must be 0 © BREG+1: BCASCREG must be1 #_BREG=2: BCASCREG can bel or2 BREG Deamal [1,02 1 Selects the number of B input registers CARRYINREG |[Deamal [1.0 1 Selects the number of CARRYIN input registers: Set tol toregister the CARRYIN inputs CARRYINEIR |[Deamal [10 1 Selects the number of CARRYINSEL input EG registers. Set to 1 to register the CARRYINSEL, impute REG Deamal [1.0 1 Selects the number of C mput registers. Set tol toregister the C inputs DREG Deamal [1.0 1 Selects the number of D input registers. Set tol toregister the D impute INMODEREG [Deamal [1,0 1 Selects the number of INMODE mput registers Set to 1 to register the INMODE inputs MASK Hee “4810000000 aSuSHEE | This 48-bit value ie used tomask out certain bite 00000 to sf during a pattem detection, When a MASK bit ie ABRALEEEEEE set tol, the corresponding pattern bit i ignored # ‘When 4 MASC bit is set 100, the pattern bits compared, REG Deamal [10 7 Selects the number of multiplier output (VM) pipeline register stages. Set tol tovuse the M Pipeline registers OPMODEREG | Deamal | 1,0 1 Selects the number of OPMODE input registers. Set tol toregister the OPMODE inputs ‘PATTERN Her “4810000000 all zeros ‘This 48-bit values used in the pattern detector 00000 to ABELEEEEE if PREG Deamal [1.0 1 Selects the number of P output registers Set tol toregister the P outputs. The registered outputs wall ndude CARRYOUT CARRYCASCOUT, MULTSIGNOUT, PATTERNB_DETECT, PATTERN _DETECT, and PCOUT, ‘SEL_MASK ‘Sang "MASE, "C MASK Selects the mazk to be used for the pattern "ROUNDING_ detector. The C and MASK settings are for MODEL", standard uses of the pattem detector (counter, "ROUNDING overflow detection, ete). ROUNDING. MODEL MODE2 (Char left shifted by 1) and ROUNDING MODE2 (C-bar let shafted by2) select special masks based off ofthe optionally repstered C port ‘Thererounding moder can be used toimplement convergent rounding in the DSPASE] slice using the pattern detector. Xilinx 7 Series FPGA Libr UG768 (v 13.4) January 18, 2012 jes Guide for HDL Designs www xilinx.com 47Chapter 4: About Design Elements £ XILINX: Attribute Type Allowed Values Default Description ‘SEL_PATIERN Sing "PATTERN, "C ‘PATTERN Selects the mput source for the pattern field, The input source can either be a 4B-bst dynamic C input ora 48-bit state PATTERN attribute Seld ‘USE_DPORT Boolean FALSE, TRUE FALSE ‘Determiner whether the preadder and theD Port are used or not USE_MULT ‘Sing. "MULTIPLY", 'DYNAMIC", "NONE" ‘MULTIPLY Selects usage of the multiplier Set to "NONE"to save power when using only the Adder/Logic Unit. The DYNAMIC" setting indicates that the user is switching between AT and AB operations on the Sand therefore need: to get the worst-case timing of the two paths ‘USE_PATIERN DETECT ‘Sing. "NO_PATDET, "PATDET ‘NO_PATDET Selects whether the pattern detector and related features are used (‘PATDET) or not used (INO_PATDET’). This atrbute is used for speed specification and Simulation Model purp ores only. USE_SIMD ‘Sing. ‘ONEAS "FOURI", Two2d' ‘ONESS Selects the mode of op eration for the adder/subtracter. The attribute setting can be one 45-bit adder mode ("ONES"), tivo 24 bit adder mode (TWO28"), or four 12-bit adder mode (FOURI2") Selecting “ONE4S” mode 4s compatible with Virtex-5 DSPIB op eration and ie not actually a true SIMD mode, Typical ‘Maltiply- Add operations are supported when the mode is se to "ONES". When either "TWO" or FOURI2" mode is selected, the anultiplier must not be ured, and USE_MULT must be set to NONE VHDL Instantiation Template Unless they already exdst, copy the following two statements and paste them before the entity declaration. NPUT => "DIRECT", Selects & urce, "DIRECT" (A port) or Ee" (ACIN port) aera = SEISEED pSlE"Ladae’ Gaon or raise) x eeeerecee™, 2a-bit mask velue for pattern detect (Inignore SELLPATTERN > "PATTERN" Select pattern value (FPATTERN” oF "C") i, Sumer cf pipeline seages for pre-edder (Gerd sens 1, somber cf pipeline srages for suowooe’ (0 ert : Somber of pipeline stoges for A (Or ior 2 : wonber cf pipeline stages for’ (Or lor 2 nes o> 1 snber cf pipeline seages for eaantst (9 or 2 118 xil Xx 7 Series FPGA Lik fries Guide for HDL Designs UG768 (v 13.4) January 18, 2012XILINX. Chapter 4: About Design Elements canmvansennes -> 1, kunber of pipeline for canmyiuser (0 oF 1) exes => 1 Number of pipeline for ¢ (0 oF 1) Res “> 1, Number of pipeline for 5 (0 oF 1) Sieisoenes => 1, Number of pipeline for TaMODE (0! oF 1) wees => 1 Number of nulipiier pipeline stages (0 o¢ 1) Sencoenes’ => 1, Nunber of pipeline for omNoDE (0 oF 1} PREG => Ie Number of pipeline for (008 1) bee inp “> voweser SIND selection (ToNEGB", "7H024", "FOURL2") 4 30-bit (each) output: Cascade Ports SSconerol: I-bit (each) output: contrel Taps! SSoate: {bir (each) output: Data Pores Cascade: 30-bit (each) input SS Gonerei: f-bit (each) dnpst Detar 30-bit (each) input: Data Ports t/clock Enable: I-bit (each) input Reset/clock Enable input: Gverflow in add/ace outpst Underfiow in sdi/acs output control inputs/seatus Bite Operation nade input PRGREERER Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG76S (v 13.4) January 18, 2012 119Chapter 4: About Design Elements XILINX. Verilog Instantiation Template J) ppp@eei: 4a-bie multi-runctional ari a Yaeries 1) xitine uot iibraries Guide, version pepaaer +1 7) Feature Control Attributes! Data aaupur (*DsRECE") TD BLINPUT ("DIRECT") + u USE_DPORT ("FALSE"), u USELMULT [TMULTEPLY"), u J) tyccern Detector Attributes: Pate AUTORESET_PATDET ("NOLRESET"), 7 Nasi (ae hueeeessese®), u PxTTERN (48"R000000000000) u SEL_MASK HRSK")» u SELLPATTERN ("PATTERN") u USELPATTERNDETECT ("NO _PATOET™), // J) naguater Gonteal attributes: Pipe! AcASERES (1), 7 ADRES (LI u ALIMODERES (2), u aRES(2), u BEASCRES(2) u BREG(2), u EARRYSHRES (2) u CARRY SHSEERES (2), u RES (2) u BRES(2) > u SROODERES (2) “ fee (21+ “ OPMODERES (2), u PRES(2), u USE_S2hb (ToMEAE™) u , Depaaet_tnse ( 7) Cascade: 30-Bit (each) outpat: ca cour (acour) , " Beour (ecour) u EARRYCASCOUT (CARRYCASCOUT) , MULTSIGNOUT (MULTSIGNOUT) + Peour (pcouF) J) conezoi: 2bit (each) output OVERFLOW (OVERFLOW) » PATTERNBDETECT (PATTERNBDETECT) , PATTERNDETECT (PATTERNDETECT) UNDERFLON (UNDERFLOW) J) pata: t-bse (each) output EARRYOUT [CARRYOUT), Pir), “ Wy cazcade: 30-bit (each) input: Cas (carnveasczn) , u (OUETSTGNIN), ” Pern (Pez u J) coneroi:’ @-bit (each) input: cone Aasmone (RLUMEDE) + 7” CARRYENSEL (CARRYINSEL) , u CEINMODE (CEINMODE) , u eux (ene + u SROODE (=1O8ODE) u ornope (ornooe) + u RETENONODE (RETENMODE) a J) pata: 30-bit each) inputs Data e Aa uw Bie), u ete, u EARRYEW (CARRYEN) ¢ u BID), a” J) Rezet/clock Enable: L-bit (each) Selects A input source, "DIRECT" (A Selects B input source; "DIRECT" (@ Select D port usage (RUE or FALSE) Select multipiier usage (*HULTIELY" 43-bit mask value for pattern detect (1-ignore) Select pattern value (TPATTERN" or "C") Enable pattern detect ("FATDET" OF "HO_PATDET") port) or Tcascape” Port) or TcASCADE™ (acon pore) (ean pore) + MovaRTC, oF "ONE fhunber of pipeisne stages hetween A/ACIN and ACOUT (0, 2 or 2) Number of pipeline stages for pre-adder (0 or 1) Number of pipeline stages for alumope (0 or 1) Number of pipeline stages for A (O) 1 oF 2) Munber cf pipeline stages between B/scit and SCOUT (0, 2 or 2) Number of pipeline stages for 8 (Q) 1 or 2) Number of pipeline stages for canavin (0 or 2) Number of pipeline stages for cARAYINSEL (0 oF 1) Munber Gf pipeline stages for © (0 or i} Munber of pipeline stages for 9 (0 or 1} Number of pipeline stages for tmmops (0! or 1) Number of sulsipiier pipeline stages (0 o¢ 1) Number of pipeline stages for ofwops (0 52 1) Munber cf pipeline stages for P (0 or 1) SIND selection (ToNEGE", "7H024", "FOURL2") Tibic cueput: overflow in ad/ace output Tobie Gucpue: Underfiow in add/asc output ‘Tobie input: Gperation mode input 120 Xilinx 7 Series FPGA Libraries Guide for HDL Designs wwwxilinx.com UG76S (v 13.4) January 18, 2012XILINX: Chapter 4: About Design Elements (cent (ceat), input enable Let stage ARES (cEA2 (CEA2) , Anput enable 2nd stage ARES (CEAD (CEAD) ; Anput enable apres (CEALUMODE (CEALUMODE) , Anput enable ZLOMODERE, ces (cee), Anput enable let stage BRES cena (ceB2), Anput enable 2nd stage BRES cec (cee), Anput enable cree (CECARRY=N (CECARRYIN) ¢ Anput enable caRayTNRES (CECTRE (CECTRL) , Anput enable CPMODERES and CARRYINSELREG cep (ce), Anput enable RES (cess (E) Anput enable RES cer (cer), Anput enable PRES RSTA(RSZA) » Anput input RSTALUCARRYIN (RSTALLCARRYIN) Anput input for cARRYINREG RSTALUMODE (RSTALUMODE) , Anput input for aLUMODERES STE (RSTB) , Anput input for BREG RSTO (RSTC) ; Anput input for cREG RSTCTRE (RSTCTRE) , Anput input for OPMODEREG and CARRYINSELRES RSTO (RSTD) , Anput input for DREG and ADRES RSTE(RSTH) , Anput input for unEc RSTP (STP) input input for PREG h JJ tnd of DSPABEL_inst instantiation For More Information See the 7 series FPGA User Documentation (User Guides ard Data Sheets). Xilinx 7 Series FPGA Libraries Guide for HDL Designs UG768 (v 13.4) January 18, 2012 www xilinx.com 121Chapter 4: About Design Elements £ XILINX: EFUSE_USR Primitive: 32-bit non-volatile design ID EFUSE_USR EFUSEUSR(St0) _ Introduction Provides intemal access to the 32 non-volatile, user-programmable eFUSE bits Port Descriptions Port Type Width Function EFUSEUSRSI O> Output 32 User FUSE register value output Design Entry Method Tnetantiation Recommended Tnference Ne (CORE Generator™ and wisards Ne Maco support Ne Available Attributes Attribute Type Allowed Values | Default Description SIMEFUSE VALUE | Hex ‘s2h00000000 te | 5200000000 ‘Value of the 32-bit non-volatile value SURE sured in simulation VHDL Instantiation Template Unless they already exdst, copy the following two statements and paste them before the entity declaration. Xilinx 7 Series FPGA Libraries Guide for HDL Designs 122 wwwxilinx.com UG768 (v 13.4) January 18, 2012€ XILINX, Chapter 4: About Design Elements Verilog Instantiation Template For More Information See the 7 series FPGA User Documentation (User Guides aud Data Sheets) Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG76S (v 13.4) January 18, 2012 123Chapter 4: About Design Elements £ XILINX: FDCE Primitive: D Flip-Flop with Clock Enable and Asynchronous Clear fh Introduction ‘This design element is a single D-type flip-flop with clock enable and asynchronous clear. When clock enable (CB) is High and asynchronous clear (CLR) is Low, the data on the data input (D) of this design element is transferred to the corresponding data output (0) during the Low-to-High clock (C) transition, When CLR is High, it overrides all other inputs and resets the data output (Q) Low. When CE is Low, clock transitions are ignored ‘This flip-flop is asynchronously cleared, outputs Low, when poweris applied. For FPGA devices, power-on conditions are simulated when global set/reset (GSR) is active GSR defaults to active High but can beinverted by adding an inverter in front of the GSR input of the STARTUP_E2 symbol, Logic Table Inputs Outputs CLR cE D c @ x x x 0 0 x x No Change 1 D T D Design Entry Method Tnetantiation Yer Inference Recommended (CORE Generator™ and wisards Ne Maco support Ne Available Attributes ‘Allowed Attribute Type _| Values Default | Description INIT Baary [10 0 ‘Sets the initial value of Q output after configuration Xilinx 7 Series FPGA Libraries Guide for HDL Designs 124 wwwxilinx.com UG768 (v 13.4) January 18, 2012€ XILINX, Chapter 4: About Design Elements VHDL Instantiation Template Unless they already exist, copy the following two statements and paste them before the entity declaration. ik Enable (posedge clk)s generic map Verilog Instantiation Template Wee a Enable. (posedge clk) a 1) xian woe 2 Guide, version 13.4 roce #1 INET (L"EO) // tnitial value of register (1'b0 oF 1°82) / ibe fete fete fete Libis Bate spot For More Information See the 7 series FPGA User Documentation (User Guides aud Data Sheets) Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG76S (v 13.4) January 18, 2012 125Chapter 4: About Design Elements £ XILINX: FDPE Primitive: D Flip-Flop with Clock Enable and Asynchronous Preset Introduction This design element is a sngleD-type flip-flop with data (D), clock enable (CE), and asynchronous preset (PRE) inputs and data output (Q). The asynchronous PRE, when High, overnides all other inputs and sets the (Q) output High. Data on the (D) input is loaded into the flip-flop when PRE is Low and CE is High on the Low-to-Hiigh clock (C) transition. When CE is Low, the clock transitions are ignored. For FPGA devices, this flip-flop is asynchronously preset, output High, when power is applied. Power-on conditions are simulated when global set/reset (GSR) is active GSR defaults to active High but can beinverted by adding an inverter in front of the GSR input of the STARTUP_E2 symbol, Logic Table Inputs Outputs PRE cE D c Q x x x 7 ° x x No Change T D 7 D Design Entry Method Tnetantiation Yer Inference Recommended (CORE Generator™ and wicards Ne Maco support Ne Available Attributes ‘Allowed Attribute Type _| Values Default | Description INIT Baary [01 1 ‘Sets the initial value of Q output after configuration Xilinx 7 Series FPGA Libraries Guide for HDL Designs 126 wwwxilinx.com UG768 (v 13.4) January 18, 2012€ XILINX, Chapter 4: About Design Elements VHDL Instantiation Template Unless they already exist, copy the following two statements and paste them before the entity declaration. ik Enable (posedge clk)s generic map Verilog Instantiation Template 1 wore ynchranous Preset and a Enable. (posedge clk) a 1) xian woe 2 Guide, version 13.4 Fore #1 IMET(L"EO) // tnitial value of register (1'b0 oF 1°82) / ibe fete fete PRE(PRE), // I-bit Aeynche Bia) Libis Bate spot J) end of FDPEinst instantiation For More Information See the 7 series FPGA User Documentation (User Guides aud Data Sheets) Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG76S (v 13.4) January 18, 2012 1.27Chapter 4: About Design Elements £ XILINX: FDRE Primitive: D Flip-Flop with Clock Enable and Synchronous Reset Introduction ‘This design clement is a singleD-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the (Q) output Low on the Low-to-High clock (C) transition, The data on the (D) input is loaded into the flip-flop when is Low and CE is High during the Low-to-High clock transition ‘This flip-flop is asynchronously cleared, outputs Low, when poweris applied. For FPGA devices, power-on conditions are simulated when global set/reset (GSR) is active. GSR defaults to active High but can beinverted by adding an inverter in front of the GSR input of the STARTUP_E2 symbol, Logic Table inputs Outputs R cE D ce @ 7 x x 7 0 ° x x No Change ° 1 D 7 D Design Entry Method Tavtantiation Yer Trference Recommended CORE Generator and wisards Ne Maco muppet Ne Available Attributes ‘Allowed Attribute Type _| Values Detautt_| Description INT Finay [0.1 ° Ses the initial value of Q output afer configuration Xilinx 7 Series FPGA Libraries Guide for HDL Designs 128 wwwxilinx.com UG768 (v 13.4) January 18, 2012€ XILINX, Chapter 4: About Design Elements VHDL Instantiation Template Unless they already exist, copy the following two statements and paste them before the entity declaration. ik Enable (posedge clk)s generic map Verilog Instantiation Template 1 eons a Enable. (posedge clk) a 1) xian woe 2 Guide, version 13.4 Fore #1 INET (LEO) // tnitial value of register (1'b0 oF 1°82) / ibe fete fete fete yee J) end of FDREnst instantiation For More Information See the 7 series FPGA User Documentation (User Guides aud Data Sheets) Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG76S (v 13.4) January 18, 2012 129Chapter 4: About Design Elements £ XILINX: FDSE Primitive: D Flip-Flop with Clock Enable and Synchronous Set Introduction FDSE is asingleD-type flip-flop with data (D), clock enable (CE), and synchronous set (5) inputs and data output (Q). The synchronous set (5) input, when High, overrides the dock enable (CE) input and sets the Q output High during the Low-to-High clock (C) transition. The data on theD input is loaded into the fip-flop when Sis Low and CE is High dunng the Low-to-High dock (C) transition. For FPGA devices, this flip-flop is asynchronously preset, output High, when power is applied. Power-on conditions are simulated when global set/reset (GSK) is active. GSR defaults to active High but can beinverted by adding an inverter in front of the GSR input of the STARTUP_E2 symbol, Logic Table Inputs Outputs s cE D c Q 1 x x T 7 ° x x No Change 0 1 D T D Design Entry Method Tnetantiation Yer Tnference Recommended (CORE Generator™ and wicards Ne Maco support Ne Available Attributes ‘Allowed Attribute Type _| Values Default | Description INIT Bmary [01 1 Sets the initial value of Q output after configuration Xilinx 7 Series FPGA Libraries Guide for HDL Designs 130 wwwxilinx.com UG768 (v 13.4) January 18, 2012€ XILINX, Chapter 4: About Design Elements VHDL Instantiation Template Unless they already exist, copy the following two statements and paste them before the entity declaration. ik Enable (posedge clk)s generic map Verilog Instantiation Template Wy a Enable. (posedge clk) a 1) xian woe 2 Guide, version 13.4 rose #1 GHIT(L"EO) // initial value of register (1'b0 or 1"B}) / ibe fete fete fete yee 1) end of FDSEinst instantiation For More Information See the 7 series FPGA User Documentation (User Guides aud Data Sheets) Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG76S (v 13.4) January 18, 2012 131Chapter 4: About Design Elements £ XILINX: FIFO18E1 Primitive: 18Kb FIFO (First-In-First-Out) Block RAM Memory FIFOWE! meoreo) ore) me D010 0080) mm —rocix RocouNT(t*:0) mmm —)roeN wrcounT(t:0) mm REGCE ALMOSTEMPTY| rst auwosteun}-— AsTAEG ewery —weerx uu} — wren ROERR| Ce Introduction 7 series devices contain several block RAM memories, each of which can be separately configured as aFIFO, an automatic error-comection RAM, or as a general-purpose 36KB or SKB RAM/ROM memory. These Block RAM memories offer fast and fleable storage of large amounts of on-chip data TheFIFO1SEI uses the FIFO control logic and the 18KB Block RAM. This primitive can be used in a4-bit wide by 4K deep, 9-bit wide by 2K deep, 18-bit wide by IK deep, or a36-bit wide by 512 deep configuration. The primitive can be configured in either synchronous or dual-clock (asynchronous) mode, with all associated FIFO flags and status signals. When using the dual-clock mode with independent docks, depending on the offset between read and wnite clock edges, the Empty, Almost Empty, Full and Almost Full flags can deassert one cycle later. Due to the asynchronous nature of the docks the simulation model only reflects the deassertion latency cycles listed in the User Guide Note For a36-bit wide by 512 deep FIFO, the 'FIFO18_36” mode must be used. For deeper or wider configurations of the FIFO, the FIFO36EI can be used. if error-corection circuitry is desired, the FIFO36E1 with "FIF036_72" mode must be used. Port Descriptions Port Type Width | Function “ALMOSTEMPTY Output 1 Programmable fag to mdicate the FIFO ie almont empty. Synchronous to RDCLK. The offset for this lag is user configurable ALMOST EMPTY_OFFSET attribute specif the threshold where this lag se triggered relative te full/empty “ALMOSTFULL Output 1 Programmable fag to indicate that the FIFO se almost fall. Synchronous to WRCLK. The offset for this lag user configurable The ALMOST FULL_OFFSET attribute specifier the threshold where this ag ss triggered relative to full/empty DISIO> Input 2 FIFO data mput bus. DIPS Input a FIFO parity data input bas, DOI Output 2 FIFO data output bus Xilinx 7 Series FPGA Libraries Guide for HDL Designs 132 wwwxilinx.com UG768 (v 13.4) January 18, 2012£ XILINX: Chapter 4: About Design Elements Port Type Width Function DOPS> Output FIFO parity data output bus EMPTY Output ‘Active high logic to indicate that the FIFO is currently, empty, No additional reads are accepted, Synchronous to RDCLK Output ‘Active high logicindicates that the FIFO i fll. RDCLK Taput TRead rising edge dock mput, To areate negative edge data reads: desenbe an inverter prior to this port. The inverter will be mapped into the programmable inverter for this blod: and not consume additional logic resources or smcur tuning penalties. Mist be tied to the same signal as WRCLK sf EN_SYN=TRUE RDCOUNTALG> Output 2 [Read counter output value. Itas synchronous with RDCLK. ‘The value vill wrap around ifthe maximum read pointer value has been reached RDEN Tnput ‘Active high FIFO read enable, When RDEN=1, data will be read to output register. When RDEN =0, read is disabled WREN and RDEN must be held Low for four clock cycles before Reset i asserted and remain Low during the Reset cya RDERR Output Indicates a read exror oosured. When the FIFO is empty, any additional read operation generates an error flag Synchronous with RDCLK, REGCE Tnput (Output register dock enable for pipelined syadironous FIFO. Only used when EN_SYNC= TRUE and D0_REG= 1. RSTREG has priority over REGCE. RST Tnput ‘Active high asynchronous reset of ll IFO fanctions dag, fand pointers, RST must be held high for 3 WRCLK and RDCLK cydes prior to operation and any subsequent revet RSTREG Tnput Output register synchronous setreset. Value (set or reset) wall correspond to the INIT attribute =p ecication, WRCLK Tnput ‘Wisite rising edge dock input, To create negative edge nites, deseibe an inverter prior tothis port. The inverter vill be mapped into the programmable inverter for this Dlodk and not consume additional logicrerources or incur ‘iaing penalties. Mast be tied tothe same signal as RDCLK, sf ENSSYNETRI WRCOUNTI10> Output 7 Write counter output value, Itis synchronous with WRCLK. ‘The value vill wrap around ifthe maxamum write pointer vale has been reached WREN Tnput “Active high FIFO waite enable, When WREN= 1, data wall bevntten tomemory. When WREN =0, write disabled WREN and RDEN must be held Low for four clock cycles before Reset sc asserted and remain Lov during the Reset oye ‘WRERR Output Indicates a wiite exror occurred. When the FIFO is fll, any additional write operation generates an error lag. Synchronous with WRCLE. Xilinx 7 Series FPGA Libr jes Guide for HDL Designs UG768 (v 13.4) January 18, 2012 www xilinx.com 133Chapter 4: About Design Elements £ XILINX: Design Entry Method Tnetantiation Yer Tnference Ne (CORE Generator™ and wisards Yer Maco support Recommended Available Attributes Attribute Type ‘Allowed Values | Default Description “ALMOST EMPTY_ Hex 1380000 to 1880060 ‘Species the amount of data OFFSET BREE contents im the RAM to trigger the ALMOST EMPTY flag. Setting determines the difference between EMPTY and ALMOSTEMPTY conditions. Must be set using hexadecimal notation. “ALMOST FULL_ He 1380000 to 1880060 Species the amount of data OFFSET BREE contents sn the RAM to trigger the ALMOST FULL flag. Setting determines the difference betureen FULL and ALMOSTFULL conditions ‘Must be set using hexadecimal notation DATA_WIDTH Decimal | 4,9, 18,36 a ‘Species the deared data width for the FIFO. ‘DO_REG Deamal [10 1 For dual-dock (asynchronous) FIFO, aust be set tol. For synchronous FIFO, DO_REG must be set t00 for flags and data to follow a standard synchronous FIFO operation. When, DO_REG is set tol, effectively a pip dlmeregicteris added tothe output fof the synchronous FIFO. Data then Ihara one dock cyde latency However, the dock-to-out timing ie improved, ENN Boolean FALSE TRUE | FALSE EN SVN denotes whether the FIFO se operating in esther dual-dock (two independent docks) or synchronous (@ single dock) mode If set to TRUE, smuust connect the same signal to WRCLK and RDCLK. If set to FALSE, uust set DO_REG=1 FIFO_MODE String "FIFOIS FIFOIS Selects the FIFO regular or wide mode "FIFOIS 36 Set to FIFOIS" when data_wdth is set 04,9 or 18. Set to FIFOIS. 36" when the wide 36-bit data path is desired FIRST_WORD_ Boolean [FALSE TRUE [FALSE IE TRUE, the first wnite tothe FIFO FALL-THROUGH snill appear on DO without a RDEN ascertion INIT He 36 bit Hex ‘36000000000 | Spear the initial value on the DO. ‘output after configuration or Global SetiReset (GSR) Xilinx 7 Series FPGA Libraries Guide for HDL Designs 134 wwwxilinx.com UG768 (v 13.4) January 18, 2012€ XILINX, Chapter 4: About Design Elements Attribute Type ‘Allowed Values | Default Description. ‘SIM_DEVICE String "VIRTEXS "7SERIES ‘Must be se to "7SERIES' in order to 7SERIES" exhibit prop er simulation behavior under all conditions SRVAL Hex 36 bit Hex 3611000000000 | Speaiies the output value of the FIFO ‘upon assertion of the DO_REGreset (RSTREG) signal. Only supported shen DO_REG= 1 and EN-SYN= ‘TRUE and RSTREGis connected toan, active signal VHDL Instantiation Template Unless they already exist, copy the following two statements and paste them before the entity declaration. 1-0) 1 signals: I-bie (each) inp! Hee bazar $2-bit (each) i Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG76S (v 13.4) January 18, 2012 135Chapter 4: About Design Elements € XILINX. Verilog instantiation Template J) erroieet: Lamb r2¥0 (3 a 5 W) xsnine won 2 sorn-Firct-out) Block RAM Memory Farogen 4 MPTY_OFFSET(13"R0080),—// ULL_OFFSET(13"NOO80), 7 Sees 1) Sece date width to Y) table output (1-0) Most be 1 i exsyn ~ rause 1) specifies “lack (FALSE) or Synchronous. (FRUE) 1) Sete mode to F2Fo18 ox FIFOIE_36 1) Secs the FIFO FRET to FALSE, TRUE 4G anise tn output pe SIMLDEVICE ("7SERTES"), Y) staat be ot co VigentEs" © SRVAL (36"R000000000) 1) sec/nesee » ql 77 Read bata? 32-bit (each) output: Read cucput “bit (each) output: Flags end other AumourEnPry (ALMOSTEMP?Y), // l-bit owepure Almost empty flag RIMOETFULL (ALMOSTFULL), // I-bit ouepur: Almost ful apry terre) Tobie cucpuc: Empey # FuLL(FUE + Tobit Gucput: Full fleg RBCOUNT (RDCCONT) » 12-bix outpur: Read count BERR [RDERR + Tobie curput: Read error TREOUNT (HRCOINT) 12-bic outputs write count RERR (WRERR Tobie cuepuc: write error cs [head control Signals: 1-bic (each) inpuc: Reed clock, enable and reset input signals RDELK IREEEE + Input: Read clock DEN (RDEN Anpur: Read enable Resor (RESCe) , Snpurs Clock ened RETIREE) Snpur! Aeyneronsu: RETREG (RETREG) + Snpur: Oueput reg J) wrsce control Signals: 1-bit (each) inpurs Nrite clock and enable input signals RELI (WRELE) ¢ Tpit input! nrive clock RREN (eRE) Tobit inpue! Write ensble S2-bie (each) input: weize input date For More Information See the 7 series FPGA User Documentation (User Guides ard Data Sheets). Xilinx 7 Series FPGA Libraries Guide for HDL Designs 136 wwwxilinx.com UG76S (v 13.4) January 18, 2012€ XILINX. Chapter 4: About Design Elements FIFO36E1 Primitive: 36Kb FIFO (First-In-First-Out) Block RAM Memory FIrOseE [Dirr0) oor(70) 04680) oes 0) mm —inwecrosrrens ecceariry(7°) mm —Jiwecrssmenn —RocouNT(120) mm —frooux wrcount(120) fmm —roen auwostempry| — —Jreace aumosteuu.t-— —rsr oe —asrres every} — —Jwacux ruut— —Jwren RocAR|} — sarrena| — wean} — Introduction 7 series devices contan several block RAM memories that can be configured as FIFOs, automatic error-correction RAM, or general-purpose 36KB or 18KB RAM/ROM memories. These Block RAM memories offer fast and fleabie storage of large amounts of on-chip data. The FIFO36E1 allows access to the Block RAM n the 36KB FIFO configurations this componant can be configured and used as adit wide by 3K deep, 9-bit by 4K deep, 18-bit by 2K deep, 36-bit wide by 1K deep, or72-bit wide by 512 deep synchronous or dua-clock (asynchronous) FIFO RAM with all associated FIFO flags, When using the dual-dlock mode with independent docks, depending on the offset betwreen read and wnite clock edges, the Empty, Almost Empty, Full and Almost Full flags can deassert one cydle later: Due to the asynchronous nature of the docks the simulation model only reflects the deassertion latency cycles listed in the User Guide Note For a72-bit wideby 512 deep FIFO, the FIFO36_72" mode must be used. For smaller configurations of the FIFO, the FIFOISE] can beused. If error-correction circuitry is desired, the 'FIFO36_72° modemust beused, Port Descriptions Port Type Width _| Function “ALMOSTEMPTY Output 1 Programmable fag to mdicate the FIFO is almont empty. ALMOST_EMPTY" OFFSET attribute specifies where to tngger thir lag “ALMOSTFULL Output 7 Programmable Sag to mdicate the FIFO is almost full, ALMOST_FULL_OFFSET attribute specifies where to ‘nigger thir flag. DBITERR Output 1 ‘Status output from ECC function toimdicate a double bit| terror waz detected. EN_ECC_READ needs to be TRUE in order touse this functionality Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www xilinx.com 137Chapter 4: About Design Elements £ XILINX: Port Type Width | Function Diss o> Tapat Gg FIFO data mput bus DIPS Input 3s FIFO panity data mput bus DOS0> Output Gg FIFO data output bus DOPE. Output FIFO panity data output bus TECCPARITYS? o> Output ‘bit data generated by the ECC encoder ured bythe ECC decoder for memory error detection and correction. EMPTY Output 1 “Active high logic toindicate that the FIFO is currently, empty, FULL Output 1 “Active high logic indicates that the FIFO ie fall INJECTDBITE RR Input 1 Inject a double bit emor ECC feature is weed INJECTSBITE RR Tnput 1 Inject a single bit error if ECC feature is ured RDCLK Input 1 Rising edge read dock RDCOUNTA2 o> Output 3 Read count RDEN Input 1 ‘Active high FIFO read enable, RDERR Output 1 Read exror occurred. REGCE Input 1 ‘Output register dock enable for pip eimed syadironous FIFO. DO-REGmust be I tose this mable RST Input 1 “Active high (FIFO logic) aryndironous reset for dual. dock FIFO), synchronous reset (Synchronous FIFO) for § CLK cys RSTREG Input 1 (Output register synchronous setireset. DO REGmust bel tose this reset ‘SBITERR Output 1 ‘Status output fom ECC function to indicate a single bit terror was detected. EN_ECC_READ needs to be TRUE in order tovuse this functionality WRCLK Input 1 Write dock and enable mput agnale WRCOUNTE2: O> Output 3 Wirte count WREN Input 1 “Active high FIFO wnte enable ‘WRERR Output 1 ‘Write error occurred, Design Entry Method Tavtantiation Yer Tnference Ne CORE Generator™ and wizards Yer Maco support Recommended Xilinx 7 Series FPGA Libraries Guide for HDL Designs 138 wonw.xiinx.com UG768 (v 13.4) January 18, 2012€ XILINX. Chapter 4: About Design Elements Available Attributes Attribute Type Allowed Values [Default | Description “ALMOST EMPTY _OFFSET | Hex 1SR0000 te 1SAIAE | 19H0060 | Specifies the amount of data contents in the RAM to trigger the ALMOST EMPTY flag ALMOST_FULL OFFSET | Hex ISRO te ISAIGE | 190080 | Specifies the amount of data contents in the RAIM to trigger the ALMOST. FULL flag, 4 Species the dened data width for the FIFO. For data widths of 72, FIFO_MODE must be set to "FIFO36 7 DO_REG Deamal [1.0 1 Enable output register to the FIFO for improved dock-to-out timing at the expense of added read latency (one pipeline delay), DO_REGmust be 1 when EN_SYN ie sef to FALSE DATA_WIDTH Deamal | 49,1856, EN_ECC READ Bodlean _| FALSE, TRUE FALSE _| Enablethe ECC decoder arcuitry EN_ECC_WRITE Boolean | FALSE, TRUE FALSE | Enablethe ECC encoder arcuitry ENN Bodlean | FALSE, TRUE FALSE | When FALSE, specifies the FIFO to beused in asynchronous mede (two independent dock) or wohen TRUE in synchronous (a angle dock) operation, FIFO_MODE ‘Sing. "FIFO36" FIFOS6" | Selects regular 'FIFOS6" or the "FIFO36_72 wide 'FIF036_72° mode. If set to "FIFO36_72', the DATA_ WIDTH attubutehas to be 72 FIRST_WORD Bodlean | FALSE, TRUE FALSE | If TRUE, the rst waite to the FIFO _FALL_THROUGH, vill appear on DO without an RDEN assertion INIT Hex 72 bit Hex ‘allzero: | Species the intial value on the DO output after configuration. ‘SIM DEVICE ‘Sing. "“VIRTEXG TSERIES’ | Mast be set to 7SERIES' im order to "7SERIES exhibit proper simulation behavior under all conditions ‘SRVAL Hex 72 bit Hex ‘allzero: | Species the output value ofthe FIFO upon assertion of the synchronous reset (RSTREG) signal. Only valid for DO_REGl. VHDL Instantiation Template Unless they already exdst, copy the following two statements and paste them before the entity declaration Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 139Chapter 4: About Design Elements € XILINX. pores => 3, Enable cutput register (1-0) must be 1 if EXSY = FALSE Specifier Fife ez Asynchronous (FALSE) of Synchroncus (TRUE) Sec/Reset value for output po! et Ibit (each) oxtps Read Sete: f-bit (each) output: Read surput data = ece 81 Abit (each) input: Error Correction Circuitry port read Control Signsis: 1-bit (each) input: Read clock, enable snd reset input signals RETREG => RETREG, Tobit input! Oueput register set/reset "write control Signals: I-bit (each) input: write clock and enable inpst signals WRCLE => REDE, AMVibieinpuct Rising edge write elock. Siysite bate: 6£-Bit (each) input: write input do Xilinx 7 Series FPGA Libraries Guide for HDL Designs 140 wwwxilinx.com UG76S (v 13.4) January 18, 2012© XILINX. Chapter 4: About Design Elements Verilog instantiation Template 1) e1ro36e1: 36mm r2¥0 a teste W) xsnine won 2 sorn-Firct-out) Block RAM Memory 1) secs the Wy Secz almost fant the 1) Sece date width to Y) enable output te) (2-0) most be 1 $8 eXsyn ~ FALSE NLRC _READ ("FALSE"), 1) enable ec decoder, FALSE, TRUE EXLECC_WRITE ("FALSE") ¢ 1) enable ec encoder, FALSE, TRUE Exevw (rane), W) Speke (raise) of synchronous (FRUE) FEFO_MODE(*FIFO36") , Wy sece mode = 3612" ORD_FALL_THRGUGH ("FALSE"), // Sets the (72"moaoo0o9000000000007,. | // anieial v. SIMLDEVICE ("TSERTES"), Was be = malation behavior ‘SRVAL (72"h000000000000000000) J) Be /Reset, L-bit (each) output: Error Correction circuil RR) Tobie cucput: bouble bit os Eeceansty (E2cPARITY) Gobi curpur: Generated SBITERR (SBITERR) + Tobie Gucput: single bit Ji head Data: 66-Oit (each) output: Read curput data (80) Garbis cucpurs Dare output BoP (BOP G-bit output: Parity dats output J) seawue 1-bic (each) output: Flags and other FIFO status outputs puanoavenery (auwosree ty) + Tobie ouput: Almost enpty flag ALMOSTFULL (ALMOSTFULL) + Tobie cueput: Almost full flag ferry teers) Tobie Suepue: Empey flag FuLL(FUE + Tobie Gueput: Full fleg RBCOUNT (RDCCONT) » Te-bie outputs Read count BERR [RDERR + Tobie cucput: Read error TREOUNT (HRCOINT) Te-bic outputs write count RERR [WRERR Tobie cuepue: ries err Jiaze Signals: L-biz (each) input: Error correction circuit INOECTDBITERR(INGECTORITERR), // 1-bir input! inject @ double Bit error inpst INSECTSBIFERR(INSECTSBITERR) + J) Read control Signals: I-bit (each) input: Read clock, enable and reset input signals RDELK IREEEE + Tbie input! Read clock DEN (RDEN Tobie input: Read enable REGCE (RESCED + Tobie inpur: Glock ensble RETIREE) Tobie inpur! Reset RETREG (RETREG) + Tobie inpurs Sueput reg :/rezet J) wrsze control Signals: I-bit| (each) inpuc? Nrite clock ond enable input signals ROLE (eREEE + Tobie dnpur: Rising edge weite clock RREN (REN) » Tobie inpur: write ensble [Presto Data: 64-bix (each) input: write input date For More Information See the 7 series FPGA User Documentation (User Guides ard Data Sheets). Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG76S (v 13.4) January 18, 2012 weww.xlline.com atChapter 4: About Design Elements £ XILINX: FRAME_ECCE2 Primitive: Configuration Frame Error Correction FRANEEOCEE Introduction ‘This design element enables the dedicated, built-in Error Correction Code (ECC) for the configuration memory of the FPGA. This element contains outputs that allow monitoring of the status of the ECC circuitry and the status of the readback CRC circuitry. Port Descriptions Port Type Width | Function CRCERROR Ouipat | Output mdicating a CRC error ECCERROR Oust Output indicating an ECC exer ECCERRORSIN GLE Ouipat | Output indicating angle-bit Frame ECC ear detected FARD50> Ouipat [26 Frame Address Register Value output SYNEITAO> Ouipat 5 Output bit address of exon SYNDROMEC2 > re (Output Tosation of exroneous bit ‘SYNDROMEVAL ID Oupst [i FrameECC ouput indicating the SYNDROME outputis valid SYNWORD6O> re ‘Word output in the frame wherean ECC error haz been detected Design Entry Method Tnvantiation Recommended Tnference Ne ‘CORE Generator and wizards Ne Maco support Ne 142 Xilinx 7 Series FPGA Libraries Guide for HDL Designs wwwxilinx.com UG768 (v 13.4) January 18, 2012€ XILINX, Chapter 4: About Design Elements Available Attributes Attribute Type Allowed Values _| Default Description FARSRC ‘String. “EFAR", FAR’ "EFAR’ Determines if the output of FAR[250] configuration register points tothe FAR or EFAR. Sets configuration option register bit CTLOU] FRAME RETIN | Sing ‘Sing reprerenting fle | ‘NONE’ “This Geis output by the ICAP_ED FILENAME name and location model and st contains Frame Data information for the Raw Bitstream, (RBM) fle. The FRAME ECCE? model will parse this Ble, calewlate ECC and output any error conditions VHDL Instantiation Template Unless they already exist, copy the following two statements and paste them before the entity declaration. generic mop ( Verilog Instantiation Template 1) wpawie_ncce2: configuration Frame Error Corres a 7 1) xsnine woe FRAME_ECCE? #1 FARSRG(EEAR") FRAvE_RET_I_FILEMAME("WONEY) // This file d= Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG76S (v 13.4) January 18, 2012 143Chapter 4: About Design Elements € XILINX. (ecoenRoR) + debie curpue, indicating NGLE EECERRORSINGLE), // I-bie supa: Soest) Sebi ouepue (seNDRoME) Te-bie outpue SYALIO (SYNDROMEVALIO), // 1-bie cuepue: SvnoRD (S¥¥HORD) T-bix outputs word output in the hb 1) end of PRR ECCE? inst For More Information See the 7 series FPGA User Documentation (User Guides ard Data Sheets). Xilinx 7 Series FPGA Libraries Guide for HDL Designs 144 wwwxilinx.com UG76S (v 13.4) January 18, 2012€ XILINX. Chapter 4: About Design Elements IBUF Primitive: Input Buffer eur p> Introduction ‘This design element is automatically inserted (inferred) by the synthesis tool to any signal directly connected. to atop-level input or in-out port of the design. You should generally let the synthesis tool infer this buffer. However, it can be instantiated into the design if required. In order to do so, connect the input port (I) directly to the associated top-level input orin-out port, and connect the output port (O) to the logic sourced by that port. Modify any necessary generic maps (VHDL) or named parameter value assignment (Verilog) in order to change the default behavior of the component Port Descriptions Port Direction Width Function ° Output 1 Baifer output 1 Input 1 Balfer input Design Entry Method Tnetantiation Yer Tnference Recommended (CORE Generator™ and wisards Ne Maco support Ne In general, this element is inferred by the synthesis tool for any specified top-level input port to the design. Itis generally not necessary to specify themin the source code However, if desired, they bemanually instantiated by either copying the instantiation code from the appropriate Libraries Guide HDL template and pasting it into the top-level entity/module of your code. It is recommended to always put all /O components on the top-level of the design to help facilitate hierarchical design methods. Connect the I port directly to the top-level input port of the design and the O port to the logic in which this inputis to source Specify the destred generto/defparam valuesin order to configure the proper behavior of the buffer. Available Attributes Attribute Type Allowed Values | Default Description TBUF_LOW_PWR| Boolean | TRUE, FALSE TRUE ‘When set to TRUE, allows for reduced power when using differential or referenced (equiring Visi) isput standards hike LVDS Or STL. A setting of FALSE demands more power but deliver: higher performance characteristic. Concult the 7 Series FPGA, SelectIO Resources User Guide for details TOSTANDARD _| Suing See Data Sheet DEFAULT _| Assigns an I/O standard to the clement Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www. inx.com 145,Chapter 4: About Design Elements € XILINX. VHDL Instantiation Template Unless they already exist, copy the following two statements and paste them before the entity declaration. <- ow power (IRUE} ve. performance (FALSE) setting for referenced 1/0 ffer input (connect directly Verilog Instantiation Template 1 x80 a = 1) xsnine 2eUF 40 npst (connect direct For More Information See the 7 series FPGA User Documentation (User Guides aud Data Sheets) Xilinx 7 Series FPGA Libraries Guide for HDL Designs 148 wwwxilinx.com UG76S (v 13.4) January 18, 2012€ XILINX. Chapter 4: About Design Elements IBUF_IBUFDISABLE Primitive: Single-ended Input Buffer with Input Disable IBUF_.BUFDISABLE Introduction ‘This design clement is an input buffer used to connect intemal logic to an extemal pin. This element indudes an input path disable as an additional power saving feature when the I/O isnot used for a sustained amount of time. Port Descriptions Port Type Width Function T Tapat T Tapat port connection Connect directly totop-level portin the design, IBUFDISABLE Input 1 Disables input path through the buifer and forces toa logic high when ‘USE_IBUFDISABLE is set to "TRUE" and this signal is asserted high If USE_IBUFDISABLE is set to FALSE" this mput is ignored and should be tied to ground, This feature is generally used toreduce ower af times when the I/O ieidle fora period of time ° Output 1 Buffer output representing theimput path to the device, Design Entry Method Tnvantiation Yer Tnference Ne CORE Gemerater™ and winards Yer ‘Macro support Ne Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www. inx.com 147Chapter 4: About Design Elements £ XILINX. Available Attributes Allowed Attribute Type _| Values Default Description TBUFLOW PWR | Suing | TRUE’ TRUE ‘Allows a trade off oflower power consumption FALSE! ‘versus highest performance when referenced I/O Handards are used TOSTANDARD Suing | SeeData Sheet | "DEFAULT | Assigns an I/O standard to the cement USEIBUFDISABLE | Suing | TRUE’ TRUE Enabler or disables the feature of IBUFDISABLE FALSE! VHDL Instantiation Template Unless they already exdst, copy the following two statements and paste them before the entity declaration. surozeasce > "TROE") Verilog Instantiation Template Tour lon Fae(Tsust), // tow pouee (TINUE) vs. pexfoomance (*raLSEM) for eeferenced 1/0 standasd IBUFDISABLE (TRUFDTSABLE) Ly to top-level port) For More Information © Seethe 7 series FPGA SelectlO Resources User Guide © Seethe 7 series FPGA User Documentation (User Guides aud Data Sheets) Xilinx 7 Series FPGA Libraries Guide for HDL Designs 148 wwwxilinx.com UG76S (v 13.4) January 18, 2012€ XILINX. Chapter 4: About Design Elements IBUF_INTERMDISABLE Primitive: Single-ended Input Buffer with Input Termination Disable and Input Disable IBUF_INTERMOISABLE INTERMOISABLE. IBUFOSABLE: 1 ° Introduction ‘This design clement is an input buffer used to connect intemal logic to an extemal pin. This element indudes an input tamination (INTERM) enable/disable as well as an input path disable as additional power saving features ‘when the I/O is not being used for a sustained amount of time. Port Descriptions Port Type Width Function 1 Tnpat 1 Input port connection. Connest direcly to top-level part an the design. IBUFDISABLE Tnpat 1 Disables input path through the buffer and force: toa logic high when USE_IBUFDISABLE ts set to "TRUE" and ‘thir signal is asserted high. IF USE_IBUFDISABLE ts set to "FALSE" this input is ignored and should be tied to ground. ‘This feature is generally used to reduce power at timer shen the I/O is idle for a period of time INTERMDISABLE Tnpat 1 Disables input tennination, This features generally weed to reduce power at times when the I/O is idle. ° Outpat [1 Buffer output reprerenting the imput path to the device Design Entry Method Tnetantiation Yer Inference Ne (CORE Generator™ and wisards Yer Maco support Ne Available Attributes Allowed Attribute Type _| Values Default Description TBUFLOWPWR | Saing | TRUE’ TRUE ‘Allows a trade off of lower power consumption "FALSE! ‘vs. highest performance when referenced 1/0 Handards are used TOSTANDARD Sting |SeeData Sheet ["DEFAULT’ | Assigns an I/O standard to the cement ‘USEIBUFDISABLE | Suing | TRUE TRUE Enabler or disables the feature of IBUFDISABLE ‘FALSE! Xilinx 7 Series FPGA Libraries Guide for HDL Designs. UG768 (v 13.4) January 18, 2012 www xilinx.com 149