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Lab 1 Introduction To Verilog HDL: Vetal Akshay Pandit (SC13B125)

This document summarizes a student's Verilog HDL lab assignment. It includes 5 questions where the student implemented various digital logic circuits using Verilog, including logic gates, half and full adders, a full subtractor, and a Gray to binary converter. For each circuit, the student provides the Verilog code and shows the output when test inputs are applied using simulation.

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35 views

Lab 1 Introduction To Verilog HDL: Vetal Akshay Pandit (SC13B125)

This document summarizes a student's Verilog HDL lab assignment. It includes 5 questions where the student implemented various digital logic circuits using Verilog, including logic gates, half and full adders, a full subtractor, and a Gray to binary converter. For each circuit, the student provides the Verilog code and shows the output when test inputs are applied using simulation.

Uploaded by

vetalap7
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Verilog HDL Lab

Lab 1
Introduction to Verilog HDL
Vetal Akshay Pandit
(SC13B125)
Sub - Verilog HDL lab

Department- B Tech Avionics

Date of submission January, 29 2015

----------------------------------------------------------------------------------------------Question 1:
Implement all logic gates using verilog HDL

Program code:
module gates (o1,o2,o3,o4,o5,o6,o7,x,y);
input x,y;
output o1,o2,o3,o4,o5,o6,o7;
assign o1=x&y;
assign o2=x^y;
assign o3=x|y;
assign o4=~x;
assign o5=~(x&y);
assign o6=~(x|y);
assign o7=x~^y;
endmodule

Verilog HDL Lab


Output by using FORCE as input:

Output by using CLOCK as input:

Verilog HDL Lab

Question 2:
Implement Half adder using Verilog HDL

Program Code :
module adder (s,c,a,b);
input a,b;
output s,c;
assign s=a^b;
assign c=a&b;
endmodule

Output by using CLOCK as input:

Output by using FORCE as input:

Verilog HDL Lab

Question 3:
Implement Full adder using Verilog HDL

Program Code:
module FullAdder (s,c,x,y,z);
input x,y,z;
output s,c;
assign s=x^y^z;
assign c=((x^y)&z)|(x&y);
endmodule

Output by using FORCE as input:

Verilog HDL Lab

Question 4:
Implement Full subtractor using Verilog HDL

Program Code:
module FullSubtractor (s,c,x,y,z);
input x,y,z;
output s,c;
assign s=x^y^z;
assign c=(~x&(y^z))|(y&z);
endmodule

Output by using FORCE as input:

Verilog HDL Lab

Question 5:
Implement Gray to Binary converter using Verilog HDL

Program Code:
module GreytoBinary (w,x,y,z,a,b,c,d);
input w,x,y,z;
output a,b,c,d;
assign a=w;
assign b=w^x;
assign c=b^y;
assign d=c^z;
endmodule

Output by using FORCE as input:

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