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    Bits Abstract

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    Srinath Santhanam
    This document describes a novel 6-bit TIQ FLASH ADC proposed by authors Vangal Srinath Santhanam and P. Saravan Prabu from PSG College of Technology, Coimbatore. The proposed ADC replaces the conventional 63-to-6 encoder with two 7-to-3 encoders, lowering circuit complexity, power dissipation, and area consumption. It also optimizes the tradeoff between bubble error tolerance and latency. This novel ADC structure offers advantages for high-speed applications by providing low power consumption, high speed, and reduced bubble errors.

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    Bits Abstract

    Uploaded by

    Srinath Santhanam
    27 views1 page
    This document describes a novel 6-bit TIQ FLASH ADC proposed by authors Vangal Srinath Santhanam and P. Saravan Prabu from PSG College of Technology, Coimbatore. The proposed ADC replaces the conventional 63-to-6 encoder with two 7-to-3 encoders, lowering circuit complexity, power dissipation, and area consumption. It also optimizes the tradeoff between bubble error tolerance and latency. This novel ADC structure offers advantages for high-speed applications by providing low power consumption, high speed, and reduced bubble errors.

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    This document describes a novel 6-bit TIQ FLASH ADC proposed by authors Vangal Srinath Santhanam and P. Saravan Prabu from PSG College of Technology, Coimbatore. The proposed ADC replaces the conventional 63-to-6 encoder with two 7-to-3 encoders, lowering circuit complexity, power dissipation, and area consumption. It also optimizes the tradeoff between bubble error tolerance and latency. This novel ADC structure offers advantages for high-speed applications by providing low power consumption, high speed, and reduced bubble errors.

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    © All Rights Reserved
    Download as DOC, PDF, TXT or read online from Scribd
    Download as doc, pdf, or txt
    27 views1 page

    Bits Abstract

    Uploaded by

    Srinath Santhanam
    This document describes a novel 6-bit TIQ FLASH ADC proposed by authors Vangal Srinath Santhanam and P. Saravan Prabu from PSG College of Technology, Coimbatore. The proposed ADC replaces the conventional 63-to-6 encoder with two 7-to-3 encoders, lowering circuit complexity, power dissipation, and area consumption. It also optimizes the tradeoff between bubble error tolerance and latency. This novel ADC structure offers advantages for high-speed applications by providing low power consumption, high speed, and reduced bubble errors.

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    ABSTRACT SHEET

    TITLE: A NOVEL TIQ FLASH ADC WITH HIGH BUBBLE ERROR


    TOLERANCE AND ULTRA SHORT LATENCY
    AUTHORS NAME: VANGAL SRINATH SANTHANAM, P.SARAVAN PRABU
    INSTITUTES NAME : P.S.G COLLEGE OF TECHNOLOGY,COIMBATORE.
    KEYWORDS: ADC(Analog To Digital Converter),TIQ(Threshold Inverter Quantisation ),Bubble
    error, Latency, Encoder
    ABSTRACT:
    A novel 6 bit TIQ FLASH ADC structure is proposed in this paper. This proposed 6 bit TIQ FLASH
    ADC replaces the 63 to 6 encoder with two 7 to 3 encoders to accomplish the encoding of the least
    significant bits and most significant bits respectively .The complexity of the physical circuit of this new
    encoder is lowered greatly. Hence both the power dissipation and area consumption are minimized. In
    this proposed 6 bit TIQ FLASH ADC ,the trade off between bubble tolerance and latency is optimized.
    This new TIQ FLASH ADC offers an excellent choice for modern high speed ADC application.
    BACKGROUND AND SCOPE OF THE PAPER:
    Adavancement in technology has made the implementation of Integrated circuits with very large number
    of devices in a single chip. At the same time, newer generations present more stringent requirements to
    the power dissipation of the Integrated circuits due to increased device density, speed and complexity.
    A need for low power VLSI chips arises from many business and technical needs. ADCs are the true
    mixed signal circuits used in most of the appliances used by the humans in their day to day life. Hence
    the reduction in the power consumption of the ADC will also mitigate the overall power consumption of
    the appliances. So the existing flash ADC architecture can be replaced with this proposed low power
    and high speed TIQ FLASH ADC.
    THE PARTICIPANTS CONTRIBUTION TO THE PAPER:
    AREA AND POWER REDUCTION: The TIQ FLASH ADC uses inverters( 2 transistors) as
    comparators instead of conventional comparators (24 transistors)and also a 63 to 6 encoder is
    replaced with two 7 to 3 encoders .So the area and the power is optimized in the proposed TIQ
    FLASH ADC.
    NOVELTY IN ENCODER PART:

    For benefits of low power and high speed ,we implement the encoders using CMOS logic gates.
    Hence this encoder eliminates BUBBLE ERROR.

    The largest latency of this encoder is exactly 3D where D is the delay of the simple two input
    CMOS gate. The latency is ultra short when compared to all other flash encoders.

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