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Floating Point Multiplier Unit: (SET ID 09SETMVD0022)

This document describes a floating point multiplier unit that supports the IEEE 754 single precision binary format. It uses a Wallace tree multiplier based on Dadda's algorithm for significand multiplication, which has a lower critical path than an array multiplier, achieving higher speeds. The unit also includes a normalization unit that outputs the mantissa in IEEE 754 format. Overflow and underflow conditions are checked but rounding is not performed for better performance. The unit was designed using Verilog HDL and its functionality was verified through ModelSim simulation.

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jayaprasadkalluri
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63 views

Floating Point Multiplier Unit: (SET ID 09SETMVD0022)

This document describes a floating point multiplier unit that supports the IEEE 754 single precision binary format. It uses a Wallace tree multiplier based on Dadda's algorithm for significand multiplication, which has a lower critical path than an array multiplier, achieving higher speeds. The unit also includes a normalization unit that outputs the mantissa in IEEE 754 format. Overflow and underflow conditions are checked but rounding is not performed for better performance. The unit was designed using Verilog HDL and its functionality was verified through ModelSim simulation.

Uploaded by

jayaprasadkalluri
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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FLOATING POINT MULTIPLIER UNIT

(SET ID 09SETMVD0022)

Submitted By:
13MVD0096 - K Jayaprasada Rao
13MVD0097 - A V Pradeep Chandra
13MVD0087 - T Sivaram Gupta

Under the guidance of :


DHANABAL R
Assistant Professor
SENSE

Abstract
In this paper we present a floating point multiplier unit that supports IEEE 754 single
precision binary format. For significand multiplication we used Wallace tree multiplier based
on Dadda algorithm instead of array multiplier for the advantage of its lowest critical path.
Dadda multiplier achieves high speed compared to array multiplier.The developed
normalization unit that supports final mantissa in IEEE 754 format. We also checked
overflow/underflow conditions and rounding is not performed for better performance. The
suggested Floating Point Unit is designed by using Verilog HDL and the functionality is
verified by using Model-sim simulation tool.
Index TermsIEEE 754, Dadda, Normalization, Overflow/Underflow

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