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Lecture 3 VLSI Design Flow

The document outlines the steps to design and fabricate an integrated circuit chip, including: 1) design specification, 2) schematic entry or HDL coding, 3) functional simulation and verification, 4) planning placement and routing, 5) timing simulation and analysis, and 6) fusing and fabrication into a physical chip. The process involves multiple iterations to refine the design until the timing and functionality specifications are met.

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Shiraz Husain
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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61 views8 pages

Lecture 3 VLSI Design Flow

The document outlines the steps to design and fabricate an integrated circuit chip, including: 1) design specification, 2) schematic entry or HDL coding, 3) functional simulation and verification, 4) planning placement and routing, 5) timing simulation and analysis, and 6) fusing and fabrication into a physical chip. The process involves multiple iterations to refine the design until the timing and functionality specifications are met.

Uploaded by

Shiraz Husain
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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VLSI

Circuits and Systems

Lecture 3: How to make a (digital) chip ?

Design Specification

Schematic Entry/ HDL


Functional Simulation/ Logical Verification
Functionally
No
Correct?
Yes
Planning Placement Routing
No(if first iterations failed Design
Routed
Yes
Timing Simulation and
Analysis
No(if first iterations failed

Timing
Specification

Fusing and Fabrication into Chip

No(if first iterations failed

No(if first iterations failed

Design Specification

Schematic Entry/ HDL

Design Specification

Algorithm
No of I/O with bits info
Functionally
No
No of bits in internal operations
Correct?
No of Clock signals
Yes
Max Clock freq used
Planning Placement Routing
Area of Chip
Power Dissipation in Chip
No(if first iterations failed Design
No(if first iterations failed
Routed
Yes
Timing Simulation and
Analysis
Functional Simulation/ Logical Verification

No(if first iterations failed

Timing
Specification

Fusing and Fabrication into Chip

No(if first iterations failed

Design Specification

Schematic Entry/ HDL

Design Entry

Functional Simulation/ Logical Verification


Functionally
No
Correct?
Yes
Planning Placement Routing
No(if first iterations failed Design
Routed
Yes
Timing Simulation and
Analysis
No(if first iterations failed

Timing
Specification

Fusing and Fabrication into Chip

Schematic
Verilog HDL
VHDL

No(if first iterations failed

No(if first iterations failed

Design Specification

Schematic Entry/ HDL

Functional Simulation

Functional Simulation/ Logical Verification


Functionally
No
Correct?
Yes
Planning Placement Routing
No(if first iterations failed Design
Routed
Yes
Timing Simulation and
Analysis
No(if first iterations failed

Timing
Specification

Fusing and Fabrication into Chip

Error Checking in HDLs


Short Circuits
Open-circuits in Schematic

No(if first iterations failed

No(if first iterations failed

Design Specification

Schematic Entry/ HDL

PPR

Functional Simulation/ Logical Verification


Functionally
No
Correct?
Yes
Planning Placement Routing
No(if first iterations failed Design
Routed
Yes
Timing Simulation and
Analysis
No(if first iterations failed

Timing
Specification

Fusing and Fabrication into Chip

Partitioning
Floor planning
Placement
Routing

No(if first iterations failed

No(if first iterations failed

Design Specification

Schematic Entry/ HDL

Timing Simulation

Functional Simulation/ Logical Verification


Functionally
No
Correct?
Yes
Planning Placement Routing
No(if first iterations failed Design
Routed
Yes
Timing Simulation and
Analysis
No(if first iterations failed

Timing
Specification

Fusing and Fabrication into Chip

Net Delays
Gate Delays

No(if first iterations failed

No(if first iterations failed

Design Specification
Fusing and Fabrication
into chip

Schematic Entry/ HDL


Functional Simulation/ Logical Verification
Functionally
No
Correct?
Yes
Planning Placement Routing
No(if first iterations failed Design
Routed
Yes
Timing Simulation and
Analysis
No(if first iterations failed

Timing
Specification

Fusing and Fabrication into Chip

ASICs
FPGAs
CPLDs
Gate Arrays
SOGs

No(if first iterations failed

No(if first iterations failed

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