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Latch Up Condition and Prevention: Figure 1 Cross Section of A CMOS IC

Latch up is a failure that can occur in a CMOS integrated circuit due to unsuitable design. It causes accidental currents that can destroy the entire circuit, so it must be prevented. Parasitic bipolar transistors form in a CMOS process that can cause a positive feedback loop. If the loop gain is greater than or equal to unity, a large current will flow and latch the circuit up until failure. Both process and design engineers must take steps to prevent latch up, such as adjusting doping levels and design rules to reduce parasitic resistances and transistor current gains.

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Ruhy Nasir
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67 views2 pages

Latch Up Condition and Prevention: Figure 1 Cross Section of A CMOS IC

Latch up is a failure that can occur in a CMOS integrated circuit due to unsuitable design. It causes accidental currents that can destroy the entire circuit, so it must be prevented. Parasitic bipolar transistors form in a CMOS process that can cause a positive feedback loop. If the loop gain is greater than or equal to unity, a large current will flow and latch the circuit up until failure. Both process and design engineers must take steps to prevent latch up, such as adjusting doping levels and design rules to reduce parasitic resistances and transistor current gains.

Uploaded by

Ruhy Nasir
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Latch up condition and prevention

In CMOS fabrication, latch-up is a failure which can arise resulting of unsuitable design. Latch-up in a
CMOS integrated circuit, causes accidental currents will probably causing with the obliteration of the
whole circuit; therefore, it must be prevented.
Figure 1 show the cross section of a two-transistor CMOS integrated circuit where the nMOS is on the
left hand side and the pMOS on the right hand side. As it can be understood from the figure, we can
talk about a scrounging pnp transistor from source of the pMOS to the p-substrate. Still a parasitic npn
transistor is formed from source of the nMOS, p-substrate and the n-well. These parasitic transistors
and finite resistances of n-well and p-substrate can be shown like Figure 2. Equivalent circuit of these
parasitic bipolar transistors is given in Figure 3.

Figure 1 Cross section of a CMOS IC

Figure 2 Parasitic bipolar transistors in a CMOS process

Latch up condition and prevention

Figure 3 Equivalent circuits formed by the parasitic transistors

As it can be clearly seen from the corresponding circuit, there is a positive feedback loop around Q1
and Q2. If a parasitic current flows through the node X and raise V x, Q2 turns on and IC2 increases
resulting VY decrease. This increases IC1 and consequently Vx increases much more. If the loop gain is
equal to or greater than unity, this situation continues until an enormous current flow through the
circuit in other words, until the circuit is latched up.

Preventing Latch-up
As described above, the loop gain of the equivalent circuit shown in Figure 3 should be lesser then
unity in order to prevent latch-ups. Thus, both of process and design engineers should take steps for
latch-up prevention. Doping levels and the other design aspects should be arranged properly in order
to have low parasitic resistances and current gain of bipolar transistors. There are specific design rules
to prevent latch-ups in different technologies

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