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Peripheral IO: Pads, ESD, IO Circuits: Design of Neuromorphic Electronic Systems

Pads interface the chip with the outside world by providing openings for bonding wires and protecting against electrostatic discharge (ESD). Pads come in different types depending on their function, such as power pads, analog input/output pads, and digital input/output pads. ESD protection structures like PN junctions are used to dissipate energy from ESD events and prevent gate overvoltage. The pad design must withstand energies up to 10mJ from potential ESD strikes like the human body model of ~10kV.

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26 views14 pages

Peripheral IO: Pads, ESD, IO Circuits: Design of Neuromorphic Electronic Systems

Pads interface the chip with the outside world by providing openings for bonding wires and protecting against electrostatic discharge (ESD). Pads come in different types depending on their function, such as power pads, analog input/output pads, and digital input/output pads. ESD protection structures like PN junctions are used to dissipate energy from ESD events and prevent gate overvoltage. The pad design must withstand energies up to 10mJ from potential ESD strikes like the human body model of ~10kV.

Uploaded by

vikramkolanu
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Peripheral IO:

Pads, ESD, IO circuits


Design of Neuromorphic Electronic
Systems

What are pads and what do they do?


Interface circuits to outside world
Provide opening in overglass and metal area for
attaching bonding wires
Protect against ESD (electro static discharge)

ESD
Your body has a capacitance of a few hundred pF
You can become charged with static electricity to
~10kV
SiO2 has a breakdown field of ~600V/m; a 10nm gate
oxide (0.5m process) will pop with a voltage of more
than 6V
ESD protection structures dissipate the ESD and prevent
gate overvoltage
The ESD protection structure must be able to dissipate
an energy of CV2=10mJ

HBM (human body model) for ESD

~10kV

Hand-held ESD tester

The bond pad


OG

OG
M2
M1
N-well

P-substrate

ESD groundedgate protection


structure
PN junctions forward bias for
over- or under-voltages.
Energy is dissipated in
junctions.
Series resistor dissipates energy

Protection transistor layout

~100 um

Pad frame

Strain relief

Types of pads

Power pads (padGND, padVDD)


Analog input pads (padIn, padInOr)
Analog output pads (padWide)
Digital IO pads (padDigIn, padDigOut)
Special pads (padBias)

Digital IO

Wide range analog output pad


-

Summary
Pads are chip IO points
They protect CMOS from ESD and drive large
off-chip loads at high speed
Pad type depends on requirements (Power,
analog input or output, digital input or output)
It is best to start with a qualified set of pads and
make changes very conservatively

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