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HW 1

This homework assignment asks students to develop a Verilog model for a seven-segment control module that displays a 4-bit binary input on two seven-segment displays, with the second display only used for inputs greater than or equal to 10. Students are also asked to develop a tester module to validate the seven-segment controller by testing it with the numbers 0, 4, 5, 10, 14, and 15.

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Kiran Kumar
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30 views

HW 1

This homework assignment asks students to develop a Verilog model for a seven-segment control module that displays a 4-bit binary input on two seven-segment displays, with the second display only used for inputs greater than or equal to 10. Students are also asked to develop a tester module to validate the seven-segment controller by testing it with the numbers 0, 4, 5, 10, 14, and 15.

Uploaded by

Kiran Kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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EEC 180B Winter 2009

HW #1
Due: Thursday 1/15/09
1. Develop a Verilog model for a seven-segment control module that takes a 4-bit binary
input (i.e, a hex digit) and shows the value on two seven-segments displays. The
second seven-segment is only used when the input is larger than or equal to 10.
2. Develop a Verilog model for a tester module that validates the functionality of your
seven-segment controller of problem 1. Test the controller with the numbers 0, 4, 5,
10, 14 and 15.

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