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Basic Flip-Flop Circuit

A flip-flop is an electronic circuit with two stable states that can serve as one bit of memory. There are different types of flip-flops that enter binary information in various ways. The basic flip-flop can be constructed from two NAND or NOR gates and has two inputs, set and reset, and two outputs, Q and its complement Q'. The D flip-flop is based on the SR flip-flop and its input D is sampled by a clock pulse to set or clear the flip-flop. The JK flip-flop refines the SR type by defining its indeterminate state, and its inputs J and K behave like the S and R inputs to set, clear,

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100% found this document useful (1 vote)
393 views2 pages

Basic Flip-Flop Circuit

A flip-flop is an electronic circuit with two stable states that can serve as one bit of memory. There are different types of flip-flops that enter binary information in various ways. The basic flip-flop can be constructed from two NAND or NOR gates and has two inputs, set and reset, and two outputs, Q and its complement Q'. The D flip-flop is based on the SR flip-flop and its input D is sampled by a clock pulse to set or clear the flip-flop. The JK flip-flop refines the SR type by defining its indeterminate state, and its inputs J and K behave like the S and R inputs to set, clear,

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Introduction

A flip-flop is a term referring to an electronic circuit (a bistable multivibrator) that has two
stable states and thereby is capable of serving as one bit of memory. A flip-flop is usually
controlled by one or two control signals and/or a gate or clock signal. The output often
includes the complement as well as the normal output. As flip-flops are implemented
electronically, they require power and ground connections.
Binary information can enter a flip-flop in a variety of ways and gives rise to different
types of flip-flops.

Theory
Basic Flip-Flop Circuit
A flip-flop circuit can be constructed from two NAND gates or two NOR gates. Each flipflop has two outputs, Q and Q', and two inputs, set and reset. This type of flip-flop is
referred to as an SR flip-flop or SR latch. When Q=1 and Q'=0, it is in the set state (or 1state). When Q=0 and Q'=1, it is in the clear state (or 0-state). The outputs Q and Q' are
complements of each other and are referred to as the normal and complement outputs,
respectively. The binary state of the flip-flop is taken to be the value of the normal
output.

(a) Logic diagram

(b) Truth table


D Flip-Flop
The D flip-flop is a modification of the clocked SR flip-flop. The D input goes directly into
the S input and the complement of the D input goes to the R input. The D input is
sampled during the occurrence of a clock pulse. If it is 1, the flip-flop is switched to the
set state (unless it was already set). If it is 0, the flip-flop switches to the clear state.

(a) Logic diagram with NAND gates

(b) Graphical symbol

(c) Transition table


JK Flip-Flop
A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR
type is defined in the JK type. Inputs J and K behave like inputs S and R to set and clear
the flip-flop. When logic 1 inputs are applied to both J and K simultaneously, the flip-flop
switches to its complement state, ie., if Q=1, it switches to Q=0 and vice versa.

(a) Logic diagram

(b) Graphical symbol

(c) Transition table

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