CMOS Analog Design Using

All-Region MOSFET Modeling

Chapter 2
Advanced MOS transistor modeling

CMOS Analog Design Using All-Region MOSFET

Modeling

Semiconductors
Four types of charge are present inside a

semiconductor: the fixed positive charge of ionized

donors, the fixed negative charge of ionized
acceptors, the positive mobile charge of holes, and
the negative mobile charge of electrons.
We consider all donors and acceptors ionized

ND N

and N A N

On this basis, the net positive charge density is

q ( N D N A p n)

CMOS Analog Design Using All-Region MOSFET

Modeling

Boltzmanns Law (1)

In equilibrium electrons and holes follow Boltzmanns

law and their concentrations (number per unit

volume) are proportional to
-( Energy / kT )

k=1.38x10-23 J/K - Boltzmann constant

T - absolute temperature (K).
electron and hole densities in equilibrium are related

to electrostatic potential by

p( 1)
e
p( 2)

q ( 1 2 )
kT

q=1.6x10-19 C
CMOS Analog Design Using All-Region MOSFET
Modeling

Boltzmanns Law (2)

n0 and p0 - equilibrium electron and hole concentrations

in the neutral bulk (=0 )

p p0 e

u / t

q
kT

p0 e

n n0 e

q
kT

n0 eu

- normalized electrostatic potential

t kT / q - thermal voltage
the mass-action law is

np n

2
i

ni - concentration of electrons (and holes) in the intrinsic

semiconductor
CMOS Analog Design Using All-Region MOSFET
Modeling

Example: Calculate the built-in potential for a Si p-n

junction with NA = 1017 atoms/cm3 and ND = 1018
atoms/cm3 ,T=300K
In equilibrium, if we choose the potential origin = 0 where the
semiconductor is intrinsic (i.e., where p0=n0=ni), then

p0 ni e

n0 ni e / t

/ t

nregion / t

Far from the junction in the n-side

n0 N D ni e

Far from the junction in the p-side

p0 N A ni e

pregion / t

The built-in potential is given by

bi n region p region

ND
t ln
ni

bi 26 ln 1015 900 mV

NA
ND N A
t ln
t ln

2
n
n

i
i

CMOS Analog Design Using All-Region MOSFET

Modeling

The two-terminal MOS structure

CMOS Analog Design Using All-Region MOSFET

Modeling

The ideal two-terminal MOS structure

(VFB=0)
A
VG

Cox

ox

tox

A - capacitor area,

Q
VG s G
Cox

+
s
_

QG QC 0

QG

QC

tox - oxide thickness

ox - permittivity of oxide

QG

QG
Cox ox

; Cox

A
A
tox

QC
VG s
Cox
CMOS Analog Design Using All-Region MOSFET
Modeling

Example: oxide capacitance

(a) Calculate the oxide capacitance per unit area for tox=
5 and 20 nm assuming ox = 3.90, where 0= 8.8510-14
F/cm is the permittivity of free space. (b) Determine the
area of a 1pF metal-oxide-metal capacitor for the two
oxide thicknesses given in (a).
Answer: (a) =690 nF/cm2 = 6.9 fF/m2 for tox=5 nm and =
172 nF/cm2= 1.7 fF/m2 for tox= 20 nm. The capacitor
areas are 145 and 580 m2 for oxide thicknesses of 5
and 20 nm, respectively.

CMOS Analog Design Using All-Region MOSFET

Modeling

The flat-band voltage

In equilibrium (with the two terminals shortened/open), the
contact potential between the gate and the semiconductor
substrate of the MOS induces charges in the gate and the
semiconductor for VGB=0.
Charges inside the insulator and at the semiconductor-insulator
interface also induce a semiconductor charge at zero bias.
The effect of the contact potential and oxide charges can be
counterbalanced by applying a gate-bulk voltage called the
flat-band voltage VFB.

VG VFB

QC
s

Cox

CMOS Analog Design Using All-Region MOSFET

Modeling

Example: flat-band voltage

(a) Determine the expression for the flat-band voltage of n+

polysilicon-gate on p-type silicon (b) Calculate the flat-band voltage
for an n+ polysilicon-gate on p-type silicon structure with NA = 1017
atoms/cm3.
Answer: (a) In equilibrium, by analogy with an n+ p junction, the
potential of the n+-region is positive with respect to that of the pregion. The flat-band condition is obtained by applying a negative
potential to the n+ gate with respect to the p-type semiconductor of
value
(b)

NA
VFB _ n p bi _ n p 0.56 V t ln

ni
VFB 0.56 V t ln 107 980 mV

CMOS Analog Design Using All-Region MOSFET

Modeling

10

Regions of operation of the MOSFET:

Accumulation (p-substrate)
VGB VFB
QC 0

G
QG
- - - - - - - - - - VGB

Qo
+
+
+
+
++++++++++++++
Holes
QC

s 0

+ accumulate in
the p-type semiconductor
surface

CMOS Analog Design Using All-Region MOSFET

Modeling

11

Regions of operation of the MOSFET:

Depletion (p-substrate)
VGB VFB
QC 0

G
QG
+ + + + + + + + +
VGB

Qo
+

- -- - - -Q - -- - - +

0 s F
Holes evacuate from the P
semiconductor surface and
acceptor ion charges
become uncovered

F = Fermi potential ( to be defined)

CMOS Analog Design Using All-Region MOSFET

Modeling

12

Regions of operation of the MOSFET:

Inversion (p-substrate)
G
QG
+ + + + + + + + +
VGB

Qo
+

- -- - ---Q - -- -- -- - - - - - +

VGB VFB
QC 0

s F

electrons
surface!

approach the

CMOS Analog Design Using All-Region MOSFET

Modeling

13

Inversion for p-type substrate

Volume charge density inside the semiconductor:

q ( p0e n0e n0 p0 )
u

Depletion of holes prevails over electron charge when

p0 e
t

n0 e or, equivalently

p0
ln( )
2
n0

mass-action
law

p02
p0
ln( 2 ) t ln( ) F
2
ni
ni

For >F the concentration of minority carriers (n)

becomes higher than that of majority carriers (p); the
semiconductor operates in the inversion region
CMOS Analog Design Using All-Region MOSFET
Modeling

14

Small-signal equivalent circuit of the

MOS capacitor

dQG
dQC

C gb

dVG
dVG

C gb

dQC
1

Cgb

dQ
d
1
d s C s

Cox
dQC Cox

1
1
1

Cc Cox

Cc dQC ds
Cc

d QB QI
ds

Cb Ci

CMOS Analog Design Using All-Region MOSFET

Modeling

15

Main approximation for compact MOS

modeling: the charge-sheet model
Minority carriers occupy a zero-thickness layer at the Si-SiO2
interface, where s

dQI
QI
Ci

d s
t

s /t

QI e

Charge-sheet + depletion approximation for the bulk charge gives

QB qN A xd 2q s N A s t
2q s N A

Cox
Cb

2 s t 2 s t

2q s N A / Cox
is the body-effect coefficient

CMOS Analog Design Using All-Region MOSFET

Modeling

16

The three-terminal MOS structure

VC

VG

n+

Carrier concentrations in Si
substrate follow Boltzmanns
law:
n, p exp(-Energy/kT)

The origin of potential is taken deep in the bulk

p p0e

q
kT

p0eu ;

n n0e

q ( VC )
kT

n0eu uC

electrons are no longer in equilibrium with holes due to the bias of

the source-bulk junction VC

pn ni2 e uC ni2 e VC / t
CMOS Analog Design Using All-Region MOSFET
Modeling

17

Small-signal equivalent circuit of the 3terminal MOS device

dQI Cb Cox Ci

dVC Ci Cb Cox

1
1
dQI
dVC
Cox Cb Ci
Approximations:
1) depletion capacitance per unit area is constant along the
channel and is calculated neglecting inversion charge
2) Charge sheet model

Ci QI / t
CMOS Analog Design Using All-Region MOSFET
Modeling

18

The linearization surface potential sa

Determination of sa s Q 0

VG

Potential balance
VG VFB

QB
sa
sa sa t

Cox

sa t VG VFB t

2
4

Cox

QI 0

Ci 0
Cb

s sa
_

QB

dsa
Cox
1

dVG Cox Cb n

CMOS Analog Design Using All-Region MOSFET

Modeling

19

Example: slope factor

For tox = 5 nm and 20 nm determine the minimum doping NA for
which the slope factor n < 1.25 at sa = 2F.
Answer: For sa=2F

2q s N A
2q s N A
Cb
n=1+
1
1

Cox
sa
2Cox
2Cox 2F
Thus, for n=1.25

0.25 2F 4Cox2
2

NA=

2q s

where F is a weak (logarithmic) function of NA. Using 2F = 0.8 V

for the first calculation, we obtain after two iterations that NA>
4.9x1015 atoms/cm3 for tox=5nm, and NA > 2.31014 atoms/cm3 for
tox=20 nm.
CMOS Analog Design Using All-Region MOSFET
Modeling

20

The Unified Charge Control Model

(UCCM) - 1

1
1
dQI
dVC
Cox Cb Ci

Approximations:
1) depletion capacitance per unit area is constant along the
channel and is calculated neglecting inversion charge
2) Charge sheet model

Ci QI / t

CMOS Analog Design Using All-Region MOSFET

Modeling

21

The Unified Charge Control Model

(UCCM) - 2

1
1
dQI
dVC
Cox Cb Ci

Ci QI / t

1
t
dQI
dVC
nCox QI

Cb
n VGB
where n 1

Cox

Integrating from an arbitrary channel potential VC to a reference

potential VP yields the unified charge control model (UCCM)

QIP
QI
QI
VP VC t
ln

t

QIP
nCox
CMOS Analog Design Using All-Region MOSFET
Modeling

QI V
QIP

C VP

22

The regional strong and weak

inversion approximations
QIP
QI
QI
VP VC t
ln
t

QIP
nCox

VP VC

VP VC

weak inversion

strong inversion

QI nCox VP VC

QI
VP VC t ln

QIP

or, equivalently

e
QI QIP

VP VC t

CMOS Analog Design Using All-Region MOSFET

Modeling

23

Example : approximate UCCM

(a) Calculate the value of the inversion charge density, normalized
to nCox t , for which the value of the voltage VP-VS
calculated using the SI approximation differs from that
calculated using UCCM by 10 %; (b) Same using the WI
approximation ; (c) comment on moderate inversion (MI)

qI (VP VC ) / t
Answer: a)
SI approximation error of less than 10 % for qI > 20
b) WI approximation

qI e

VP VC t

WI approximation error of less than 10 % for qI < 0.22.

(c) MI region : SI and WI approximations give errors greater than
10 % for the control voltage VP-VS. The inversion charge
density variation from the lower to the upper limit of the MI
region is approximately two orders of magnitude (20/0.22).
CMOS Analog Design Using All-Region MOSFET
Modeling

24

The pinch-off charge density

The channel charge density corresponding to the effective
channel capacitance times the thermal voltage, or thermal
charge, defines pinch-off

(Cox
Cb )t nCox
t
QIP
The name pinch-off is retained herein for historical reasons
and means the channel potential corresponding to a small
(but well-defined) amount of carriers in the channel.

CMOS Analog Design Using All-Region MOSFET

Modeling

25

The pinch-off voltage VP

The channel-to-substrate voltage (VC) for which the channel
charge density equals is called the pinch-off voltage VP.
in weak
inversion

2 V /
2 V /
QI Cbt e sa F C t Cox (n 1)t e sa F C t

UCCM is
asymptotically correct
in weak inversion if

n
VP sa 2F t 1 ln

VP sa 2F

CMOS Analog Design Using All-Region MOSFET

Modeling

26

Threshold voltage
Equilibrium threshold voltage VT0, for VC=0:
nCox
t
Gate voltage for which QI QIP
or
Gate voltage for which VP=0

VP sa 2F
Recalling that

it follows that

VG VFB sa Cox sa t
VT 0 VFB 2F 2F
CMOS Analog Design Using All-Region MOSFET
Modeling

27

Example: threshold voltage

+

Estimate VT0 for an n-channel transistor with n polysilicon gate,

NA=1017 atoms/cm3 and tox=5 nm.
Answer: The flat-band voltage (slide 10) is -0.98 V; F=0.419; Cox=
690 nF/cm2. The body-effect factor is 2q s N A / Cox 0.264 V

VT 0 VFB 2F 2F = 0.98 0.838 0.264 0.838= 0.1V

For this low value of the threshold voltage, the off-current (for VGS=0)
is too high for digital circuits.
Solution to control the magnitude of the threshold voltage without an
exaggerated increase in the slope factor
a non-uniform
high-low channel doping.

CMOS Analog Design Using All-Region MOSFET

Modeling

28

Pinch-off voltage vs. gate voltage

4.0

4.00E+00

3.0

2.0

1.5

1.5

2.0

2.00E+00

1.0

1.0

1.00E+00

VP

0.00E+00

Cox
dVP dsa
1

dVG dVG Cb Cox n

-1.0

-1.00E+00
0.00E+00

1.00E+00

2.00E+00

3.00E+00

4.00E+00

5.00E+00

slope factor

pinch-off voltage

3.00E+00

0.5

0.5

0
6.00E+00

1.0
2.0
3.0
4.0
5.0 VG (V)
VT0 (equilibrium threshold voltage)

Useful approximation: VP

VGB VT0
n

CMOS Analog Design Using All-Region MOSFET

Modeling

29

The MOS transistor

W xi

xi

0 0

I D J n dxdz W J n dx
CMOS Analog Design Using All-Region MOSFET
Modeling

30

Exact I-V model of the MOSFET (1)

d
dn
J n qn n qDn
dy
dy
drift

n n0e

q ( VC )
kT

u uC

n0e

Using the Einstein relationship

VS VC VD

diffusion

dn n d dVC

dy t dy dy

Dn nt

d dVC
dVC
d
J n qn n
qn n

qn n
dy
dy
dy dy

CMOS Analog Design Using All-Region MOSFET

Modeling

31

Exact I-V model of the MOSFET (2)

W xi

xi

I D J n dxdz W J n dx
0 0

dVC
J n qn n
dy

dVC
I D qW nn
dx
dy
0
xi

xi

QI q ndx
0

I D W nQI

dVC
dy

Since the current is constant along the channel

ID

nW VD
L

QI dVC

L is the channel length

VS

CMOS Analog Design Using All-Region MOSFET

Modeling

32

Charge-sheet formula for the current

Ci

dVC

QI

VG

dQI

d s

dQI Ci dVC ds
dQI
dVC ds t
QI

I D I drift I diff

nWQI

CMOS Analog Design Using All-Region MOSFET

Modeling

dVC
J n qn n
dy

ds
dQI
nW t
dy
dy

33

Charge control compact model (1)

VG
dQI

dVC

Ci

d s
dQI
I D nWQI
nW t
dy
dy

Cox
d s
_

Cb

Cb )ds nCox
ds
dQI (Cox

dQB

nW

dQI
)
ID
(QI t nCox

nCox
dy

Integrating along the channel yields

ID

2 QID
2
nW QIS

2nCox

QID

t QIS

CMOS Analog Design Using All-Region MOSFET

Modeling

34

Charge control compact model (2)

drift +
ID

2 QID
2
nW QIS

2nCox

diffusion

Q QID
Q QID
QID
nW IS
t IS
t QIS
nCox

2
nC
L

ox

virtual charge

ds
dQI nCox

QID

QIS
s 0 sL

I D nW
nCoxt

2
L

average
charge density

CMOS Analog Design Using All-Region MOSFET

Modeling

average
electric field

35

Charge control compact model (3)

To emphasize the symmetry of the rectangular geometry
MOSFET

ID IF IR
I F ( R)

Q
W
IS ( D )
( D)
n
t QIS

L
2nCox

(compare with Ebers-Moll model of the BJT)

CMOS Analog Design Using All-Region MOSFET

Modeling

36

Drain current vs. gate-to-bulk voltage

CMOS Analog Design Using All-Region MOSFET

Modeling

37

Comparing UCCM and the surface potential

model with exact numerical solution of
Poisson equation

CMOS Analog Design Using All-Region MOSFET

Modeling

38

Modeling the bulk charge from

accumulation to inversion
s t (es / t 1)
Charge-sheet approximation QB sgn(s )Cox

VG VFB s QI QB / Cox

Potential balance

sa s Q 0
I

VG VFB sa 2 2 sa t e
1 dQB
n 1
Cox ds

s sa

sa

sgn sa 1 esa / t
Cb
1
1
Cox
2 sa t esa t 1

CMOS Analog Design Using All-Region MOSFET

Modeling

39

Modeling from accumulation to inversion:

Surface potential and pinch-off voltage (VP)

CMOS Analog Design Using All-Region MOSFET

Modeling

40

Transistor symmetry
1.

I D I D VG ,VS ,VD

VG

Voltages referenced to local substrate: VS

VG VGB

VS VSB

VD

VD VDB

2. Symmetry

I D VG ,V1,V2 I D VG ,V2 ,V1

ID

B
V1

ID V2
VG

CMOS Analog Design Using All-Region MOSFET

Modeling

41

Normalization
3. For a long-channel MOSFET

W
I D I F I R I S i f ir I SQ f VG ,VS f VG ,VD
L

I F R I S qIS D 2 2qIS D
qIS D QIS D / nCox t

ID

i f r I F R / I S

t2 W

W
I S Cox n
I SQ
2 L
L

IF IR

IS and ISQ are the normalization (specific)

current and the sheet normalization
current, slightly dependent on bias.
CMOS Analog Design Using All-Region MOSFET
Modeling

42

Forward and reverse currents

Long-channel MOSFET

I D I F I R I (VG ,VS ) I (VG ,VD )

IF: forward current

IR: reverse current

IR=
IF=

CMOS Analog Design Using All-Region MOSFET

Modeling

43

Specific current
The specific (normalization) current

I S Cox n

t2 W
2 L

I SQ

W
L

ISQ : process parameter slightly dependent on VG and T

ISQ 25 nA (p-channel)
ISQ 75 nA (n-channel)
in 0.35 m CMOS

CMOS Analog Design Using All-Region MOSFET

Modeling

44

Pinch-off voltage and slope factor (1)

UCCM

( D) 1 ln qIS
( D)
VP VS ( D) t qIS

qIS ( D) 1 i f ( r ) 1

&

VP VG VT 0 2F 2F
2
2

Linearization:
VP

Slope =1

Slope =1/n

VP VP 0

VG VG 0
n VG 0

n VG 0 1

2 VP 0 2F

In particular:

VP0

VP
VT0

VG0

VG

VG VT 0
n VT 0

n VT 0 1

CMOS Analog Design Using All-Region MOSFET

Modeling

2 2F
45

Pinch-off voltage and slope factor (2)

Determination of the pinch-off voltage and the slope factor as

functions of VG. NMOS transistor W=20 m, L=2 m, 0.18 m
CMOS technology.

CMOS Analog Design Using All-Region MOSFET

Modeling

46

The I-V relationship (1)

VP VS t 1 i f 2 ln

1 i f 1

1,00E-03

10-3

VD = VG

ID (A)

VD

1,00E-04

ID

VS = 0 V

1,00E-05

0.5
1.0

10-6

1,00E-06

1.5

VG

2.0

VS

1,00E-07

2.5
3.0

1,00E-08

-9
1,00E-09
10
0,00E+00
0

5,00E-01

1,00E+00

1,50E+00

2,00E+00

2,50E+00

3,00E+00

3,50E+00

4,00E+00

4,50E+00

4 VG (V)

Common-source characteristics
CMOS Analog Design Using All-Region MOSFET
Modeling

47

The I-V relationship (2)

VP VS t 1 i f 2 ln

10-3

ID (A)

1 i f (r ) 1

VD = VG
VG = 4.8 V
VD
ID

10-6

VG
0.8 V

10-9

VS

VS (V)

Common-gate characteristics VG=0.8, 1.2, 1.6,

2.0, 2.4, 3.0, 3.6, 4.2, and 4.8 V
CMOS Analog Design Using All-Region MOSFET
Modeling

48

Weak inversion model

Weak inversion

if(r)<1

VG VT 0
VS ( D ) t 1 i f ( r ) 2 ln

n
-1

I D I0

VG VT 0

V
S / t

1 e VDS / t

I0 n

1 i f (r ) 1

if(r)/2
W
t2e1 2 I S e1
nCox
L

CMOS Analog Design Using All-Region MOSFET

Modeling

49

Strong inversion model (1)

VG VT 0
VS ( D ) t 1 i f ( r ) 2 ln

Strong inversion

if(r)>>1

1 i f (r ) 1

VG VT 0
VS ( D ) t i f ( r ) t I F ( R ) I S
n

I D I F I R nCox
Moderate inversion
1<if(r) <100

W
2
2

nV

nV

G
T0
S
G
T0
D

2nL
Both sqrt(.) and ln(.) terms are important

CMOS Analog Design Using All-Region MOSFET

Modeling

50

Strong inversion model (2)

ID

VDS

VG
ID/IF
1

VDSsat=VP=(VG-VT0)/n

VDS

Transistor output characteristic

CMOS Analog Design Using All-Region MOSFET
Modeling

51

Strong inversion model (3)

ID

ID

Cox W
2n L

VG VT 0

ID

ID

Cox W
2n L

VG VT 0 nVS

SCE, , n,
model
VT0

VDD

VG VT 0

VG

VS

VDD

ID

ID

VG

VG
VS

CMOS Analog Design Using All-Region MOSFET

Modeling

52

Universal output characteristics

1 i f 1
qIS

ln
qIS qID
1 i f 1 ir ln

t
qID
1 ir 1

VDS

(o): measured
(): model

(a) if= 4.5x 10-2 (VG=0.7 V); (b) if= 65(VG= 1.2 V); (c) if= 9.5x102 (VG= 2.0 V); (d) if=
3.1x 103 (VG= 2.8 V); (e) if= 6.8x 103 (VG= 3.6 V); (f) if= 1.2x 104 (VG= 4.4 V).
CMOS Analog Design Using All-Region MOSFET
Modeling

53

Saturation voltage
/ qIS
Saturation voltage (VDSsat) VDS such that qID

VDSsat t ln 1 1

1 i f 1

CMOS Analog Design Using All-Region MOSFET

Modeling

is the saturation level

54

Transconductances - 1
Transconductances

I D g mg VG g ms VS g md V D g mb V B

g mg g ms g md g mb 0

g mg

Calculation of gms

IF IR
I
W
gms
F QIS
VS
VS
L
g md

g mg I S
UCCM

(i f ir )
VG

I D
I
I
I
, g ms D , g md D , g mb D
VG
VS
V D
V B

i f
VG

QID
L

i f
nVS

ir
i
r
VG
nVD

Pao-Sah ID (UCCM)

g mg

g mg

g ms g md

n
g
in saturation
ms
n

CMOS Analog Design Using All-Region MOSFET

Modeling

55

Transconductances - 2

VDD
ID
VG
VS

Source transconductance VG= 0.8, 1.2, 1.6, 2.0, 2.4, 3.0, 3.6,
4.2, and 4.8 V
(W=L=25 m, tox=280 )
CMOS Analog Design Using All-Region MOSFET
Modeling

56

Transconductances - 3
VDD
ID

VG

VS

Gate transconductance VS= 0, 0.5, 1.0,1.5, 2.0, 2.5, and 3.0 V .

W=L=25 m, tox=280
CMOS Analog Design Using All-Region MOSFET
Modeling

57

The transconductance-to-current ratio - 1

Transconductance
-to-current ratio

g ms( d )t
I F ( R)

2
1 i f (r ) 1

WI (if <1)

2
i f (r )

SI (if >>1)

102

gms/IF
W=25 m
101

tox = 28 nm (IS = 26 nA)

L=25 m, tox= 280

tox = 5.5 nm (IS = 111 nA)

L=20 m, tox= 55

Seqncia1

Seqncia2

model

Seqncia3

100
10-4

1,00E-03

10-2

1,00E-01

100

102

if

104

CMOS Analog Design Using All-Region MOSFET

Modeling

58

The transconductance-to-current ratio - 2

Transconductance
-to-current ratio

g ms( d )t

I F ( R)

2
1 i f (r ) 1

WI (if <1)

2
i f (r )

SI (if >>1)

1,00E+02
2

10

gms/IF

W=L=25 m, tox= 280

= 1.0 V (IS = 33 nA)

Seqncia1
GB
1,00E+01
1

10

VGB = 2.0 V (IS = 26 nA)

Seqncia2

VGB = 3.0 V (IS = 24 nA)

Seqncia3

model

Seqncia4

1,00E+00
0
1,00E-04
-4

10

10

1,00E-03

1,00E-02
-2

10

1,00E-01

1,00E+00
0

10

1,00E+01

1,00E+02
2

10

if

1,00E+03

1,00E+04
4

10

CMOS Analog Design Using All-Region MOSFET

Modeling

59

The transconductance-to-current ratio - 3

g ms( d )t

Transconductance
-to-current ratio
101002

I F ( R)

2
1 i f (r ) 1

WI (if <1)

2
i f (r )

SI (if >>1)

gms/IF

10101

L = 25 m (IS = 26 nA)

W=25 m, tox= 280

Seqncia1

L = 2.5 m (IS = 260 nA)

Seqncia2

model

Seqncia3

0
1
101,00E-04
10-4

1,00E-03

1,00E-02

10-2

1,00E-01

1,00E+00

100

1,00E+01

1,00E+02

102

1,00E+03

if

1,00E+04

104

1,00E+05

CMOS Analog Design Using All-Region MOSFET

Modeling

60

The low-frequency small-signal model

G

g md v d
id
S

g mb vb

g ms v s
g mg v g
B
CMOS Analog Design Using All-Region MOSFET
Modeling

61

Quasi-static charge-conserving model

The current entering each terminal of the transistor is split into

a transport component (IT) and a capacitive charging term.

dQD
I D (t ) IT (t )
dt

W VD t
I T (t ) n
QI (VC ) dVC
L VS t

Quasi-static approximation: To calculate the stored charges

we suppose that the charge stored in the transistor depends

only on the instantaneous terminal voltages
Neglecting leakage currents

QG W QG dy
0
L

QB W QB dy
0

dQG
IG (t )
dt
dQB
I B (t )
dt

CMOS Analog Design Using All-Region MOSFET

Modeling

62

Ward-Dutton partition of the channel

charge
L

y
QS W (1 )QI dy
L
0

dQS
I S (t ) IT (t )
dt

QD W

y
QI dy
L

dQD
I D (t ) IT (t )
dt
dQD dQS dQI
I D (t ) I S (t )

dt
dt
dt

As expected
L

QI W QI dy is the total inversion charge stored

0

in the channel
CMOS Analog Design Using All-Region MOSFET
Modeling

63

Calculation of stored charge - 1

I D I drift I diff
d s
dQI
nWQI
nW t
dy
dy

ds
dQI nCox

nW
dy '
QI nCox t dQI
nCox I D

It is convenient to define
dy

nW
'
nCox
ID

t
QIt QI nCox
QIt dQIt

CMOS Analog Design Using All-Region MOSFET

Modeling

64

Calculation of stored charge - 2

L

QI W QI dy
0

dy

nW
'
nCox
ID

QI

QIt dQIt

( D ) nCox
t
QF ( R ) QIS
Using

or

ID

nC

Q
dQ

ox t It
It
QR It
I D nCox

QI

nt (W / L)

2nCox t

nW 2 QF

nW 2 QR3 QF3

ID
nCox

QF2 QR2

QR2 QF2
t
nCox

we find that

2 QF2 QF QR QR2

nCoxt
Q I WL

3
Q

Q
F
R

2 QIS
QID
QID
2 ) nCox
t (QIS
QID
)
2 3(QIS
QI WL
QID
2nCox
t
QIS

CMOS Analog Design Using All-Region MOSFET

Modeling

In weak inversion

QI WL

QID
)
(QIS
2

In strong inversion &

saturation

QI 2 3WLQIS
65

Total inversion, source and drain charges

Channel linearity
coefficient

nCox
t
QR QID

nCox
t
QF QIS

=1 in WI
0 in SI sat
=1 in SI for VDS=0

2 1 2

nCox
t ) nCox
t
QI WL
(QIS
3 1

6 12 8 2 4 3

n
nCox
t ) Cox
t
QS WL
(QIS
2
2

15 1
4 8 12 2 6 3

n
nCox
t ) Cox
t
QD WL
(QIS
2
2

15 1

CMOS Analog Design Using All-Region MOSFET

Modeling

66

Capacitive coefficients - 1
Using the quasi-static approximation
Q j dVG Q j dVS Q j dVD Q j dVB

dt
VG dt
VS dt VD dt
VB dt

dQ j

Defining

Qj
C jk
Vk

jk
0

Qj
C jj
Vj

dQ G / dt C gg C gs C gd C gb dVG / dt

/
dt
dQ
dV
/
dt

C
C
C

C
sg
ss
sd
sb
S
S

dQ / dt C dg C ds
C dd C db dVD / dt
D

dV / dt
dQ / dt C

B
bg C bs C bd C bb B

CMOS Analog Design Using All-Region MOSFET

Modeling

67

Capacitive coefficients - 2
The 16 capacitive coefficients are not linearly

independent
Assume

VG t VS t VD t VB t V (t )

Under equal terminal voltage variations, the charging

currents are zero. For the gate charging current, e.g.,
we have
dQ G
dV
(Cgg Cgs Cgd Cgb )
0
dt
dt

C gg C gs C gd C gb

Similarly, for S, D, and B nodes

Cdd Cdg Cds Cdb

Css Csg Csd Csb

Cbb Cbg Cbs Cbd

CMOS Analog Design Using All-Region MOSFET

Modeling

68

Capacitive coefficients - 3
Assume that
dVS dVD dVB

0
dt
dt
dt

d QG
dVG d Q S
dVG
C gg
,
Csg
,
dt
dt
dt
dt
dQD
dVG d Q B
dV
Cdg
,
Cbg G
dt
dt
dt
dt

The sum of all the charging currents is

d QG d Q S d Q D d Q B
dVG

(Cgg Csg Cdg Cbg )

dt
dt
dt
dt
dt

Charge conservation,
d(QS+QD+QB+QG)/dt=0

C gg Csg Cdg Cbg

CMOS Analog Design Using All-Region MOSFET

Modeling

69

Capacitive coefficients - 4
Linear relationships between capacitive

coefficients

C gg C gs C gd C gb Csg Cdg Cbg

Css Csg Csd Csb C gs Cds Cbs
Cdd Cdg Cds Cdb C gd Csd Cbd
Cbb Cbg Cbs Cbd C gb Csb Cdb
Only nine out of the sixteen capacitive

coefficients are linearly independent

CMOS Analog Design Using All-Region MOSFET
Modeling

70

A complete set of 9 capacitive coefficients

for the MOSFET
2
1 2 qIS
Cgs Cox
2
3
1 1 qIS
Cgd

2
2
2 qID

Cox
2
3
1

1 qID

Csd

Cbs ( d ) (n 1)C gs ( d )
Cgb Cgb

n 1

(Cox Cgs Cgd )

n

4
3 2 3 qID
nCox
3
15
1 1 qID

4
1 3 2 qIS
Cds nCox
3
15
1 1 qIS

Cdg Cgd Cm (Csd Cds ) / n

CMOS Analog Design Using All-Region MOSFET
Modeling

71

Simplified small-signal MOSFET model

G

gmd vDB Csd

Cgs

dvDB
dt

Cg
d

Cbs

dv
g mg vGB Cm GB
dt

Cbd

g ms vSB Cds
B

Cgb

dvSB
dt

CMOS Analog Design Using All-Region MOSFET

Modeling

72

The five capacitances of the simplified

model

Intrinsic capacitances simulated from (___) the charge-based and (o) from
the S- model (NMOS transistor, tox= 250, NA=2x1016 cm-3, and VT0=0.7V.
CMOS Analog Design Using All-Region MOSFET
Modeling

73

Capacitances of extrinsic transistor - 1

CMOS Analog Design Using All-Region MOSFET

Modeling

74

Capacitances of extrinsic transistor - 2

CMOS Analog Design Using All-Region MOSFET

Modeling

75

Non-quasi-static (NQS) small-signal

model
Channel segmentation: representation of the MOSFET
as a series combination of short transistors

CMOS Analog Design Using All-Region MOSFET

Modeling

76

Simplified high-frequency MOSFET model

G

Cgs

1 j 1 2

g md vd
1 j 1

1 j 1 3

g mg vg
Cbs

1 j 1 2

Cgd

1 j 1

Cgb

1 j 1 4

Cgb

Cbd

g ms vs
1 j 1

CMOS Analog Design Using All-Region MOSFET

Modeling

1 j 1 3

77

Time constants of the NQS MOSFET

model

4 1 3 2
1
1 qIS 15 1 3

1 2 8 5
2
1 qIS 15 (1 )2 (1 2 )
2

L2

1 5 8 2 2
3
1 qIS 15 (1 ) 2(2 )

CMOS Analog Design Using All-Region MOSFET

Modeling

78

Quasi-static small-signal model

1<<1

2(3)<<1

non-quasi-static model
reduces to the five-capacitor model
G

C gs

g md vDB

C gd

g mg vGB
S

Cbs

Cgb

g ms vSB

Cbd

B
CMOS Analog Design Using All-Region MOSFET
Modeling

79

Example: Small-signal parameters

Calculate ID, VDSsat and small-signal parameters of a saturated nchannel MOSFET in 0.35 m technology at if = 3 with
VSB= 0. W=10 m, L=1 m, tox=7 nm, n=1.2, n=400 cm2/V-s at 300 K.

Answer:

Cox =493 nF/cm2 and I SH nCox nt2 / 2= 80 nA.

gmd = 0, Cgd = 0 and Cbd = 0 since the transistor is saturated.

I D I F (W / L) I SH i f 10 80 3 2.4 A

VDSsat t 3 1 i f 26(3 2) 130 mV

QIS
qIS
1 i f 1 1 3 1 1
t
nCox

g mg (2 I S / nt )

1 i f 1

g mg

2 10 80 nA
51 A/V
1.2 0.026 V

CMOS Analog Design Using All-Region MOSFET

Modeling

80

Example: Small-signal parameters (continued)

2
1 2 qIS
Cgs Cox
2
3
1 1 qIS

Cgb

qID 1
1

1
qIS 1 qIS

n 1

(Cox Cgs Cgd )

n

=1/(1+1)=0.5

49 fF
Cox WLCox

2
11
1
Cgs 49
14.5 fF
2
3 10.5 1 1
0.2
Cgb
(49 14.5 0) 5.75 fF
1.2

CMOS Analog Design Using All-Region MOSFET

Modeling

81

Intrinsic transition frequency

fT

g mg

2 Cgs Cgb

g ms

2 n Cgs Cgb

t
fT
2
2
2 L

1 i f 1

CMOS Analog Design Using All-Region MOSFET

Modeling

82

Example: Transition frequency

Determine the inversion level for which the transition
frequency of a minimum (nominal) length NMOS
transistor in the 0.35 m technology is 10 GHz at room
Answer:

Assuming that n=1.2 and n = 400 cm2/V-s at 300 K

it follows that

i f 1 L fT / nt
2

1 21

Thus, operation in moderate inversion can be

considered for a design at 1 GHz, for example.
CMOS Analog Design Using All-Region MOSFET
Modeling

83

Main short-channel effects

Mobility dependence on the electric field

Channel length modulation

Drain-induced barrier lowering
Velocity saturation

CMOS Analog Design Using All-Region MOSFET

Modeling

84

Mobility dependence on the electric field

Inclusion of mobility variations in compact modeling: the constant
mobility is substituted with an effective mobility, which depends
on the applied voltages.

eff

0
QBS
QIS
QBD
QID

1

s
s

0, the low-field mobility and , the scattering constant, are fitting

parameters

Another simplification: the effective transversal field is assumed

constant along the channel and equal to its value at pinch-off.
0
eff
Q
1 Ba
s
CMOS Analog Design Using All-Region MOSFET
Modeling

85

Channel length modulation

The dependence of the effective channel length on the drain-to-source
voltage is referred to as the channel length modulation (CLM).
D

ID

VDS VDSsat
L LC ln 1

VDSsat

VDS

L
0

2
qIS qID

1
qID

ID IS
qIS

L 1 qIS qID

1
L
CMOS Analog Design Using All-Region MOSFET
Modeling

Le

86

Drain-induced barrier lowering (DIBL)

An increase in the drain voltage produces an increase in the

surface potential in the channel and, consequently, a reduction

in the potential barrier seen by the electrons at the source (
DIBL).
The inclusion of the DIBL effect in MOSFET models is generally

through the threshold voltage.

VT VT ,lc

L
6t ox
2bi VBS VDS exp

d1
4d 1

VT VT ,lc bi VSB bi VDB

CMOS Analog Design Using All-Region MOSFET
Modeling

87

Velocity saturation effects - 1

s
1

F
FC

s
s d S
vsat dy

dS
F (longitudinal field)
dy
Allows analytical
integration for ID

v
vsat
vsat

FC

FC
CMOS Analog Design Using All-Region MOSFET
Modeling

F
88

Velocity saturation effects - 2

dQI nCox ds

I D WQI

dVC
dy

s
s

nCox vsat

sWQI

dQI
dy

dQI
ID
dQI dy
1
1
FC dy
nCox

t dVC
dQI 1

dy nCox QI dy

1
t

nC
Q
I
ox

QIS

QID

QIS

ID
QIP QID

Q QIS
L
nCox
2

1 ID

LFC nCox

sW

CMOS Analog Design Using All-Region MOSFET

Modeling

89

Velocity saturation effects - 3

Normalized current vs.
normalized charge densities

t
qI QI / nCox
IS

t2

s nCox
L
2

iD I D / I S

qIS qID 2

iD
qIS qID

1 qIS qID

st / L

vsat

Normalization (specific) current

short-channel parameter : ratio of diffusion-related

velocity to saturation velocity

CMOS Analog Design Using All-Region MOSFET

Modeling

90

Velocity saturation effects - 4

Saturation: The minimum amount of electron charge flowing at
the saturation velocity, required to sustain the current is

QIDSAT
I D / Wvsat

qIS 1 qIDsat
1 qIDsat

ID

QI

QIS

QID

VDS

QIDSAT

0
CMOS Analog Design Using All-Region MOSFET
Modeling

91

Velocity saturation effects - 5

2

qIS 1 qIDsat
1 qIDsat

QIDSAT QIS

1
Short channel

st L

Long channel

strong
inversion

weak
inversion

vsat
10-2

100

102

104

QIS nCox t
CMOS Analog Design Using All-Region MOSFET
Modeling

92

Small dimension effects on charges

and capacitances
I D WQI

dVC
dy

s
s

nCox vsat

dQI
dy

t dVC
dQI 1

dy nCox QI dy

sW

ID
t
dy
QI nCox
ID
nCox
Wvsat

CMOS Analog Design Using All-Region MOSFET

Modeling

dQI

93

Virtual charge formalism - 1

Virtual inversion charge density

t
QV QI nCox

ID
Wvsat

inversion +pinch off -saturation charge

densities
Along the channel

sW

dQV dQI

ID

dy
Q

nC

ox t
ID I
nCox
Wvsat

sW

dQ

QV dQV
I
ID
nCox

CMOS Analog Design Using All-Region MOSFET

Modeling

94

Virtual charge formalism -2

dQV
d s
ID
QV
sWQV

nCox
dy
dy

sW

The drift of the virtual charge produces the

same current as the actual movement of
the real charge, which includes drift,
diffusion and velocity saturation

CMOS Analog Design Using All-Region

All Region MOSFET
Modeling

95

Channel linearity coefficient with vsat

dQV
QV
The integration of I D

nCox
dy

sW

from

source to drain results in

ID
where

2 QVD
2
sW QVS

L
Cox

2n

I D0 1 2

nCox
t I D Wvsat

QID
QVD

nCox
t I D Wvsat
QVS
QIS

CMOS Analog Design Using All-Region MOSFET

Modeling

96

Stored charges including vsat

The stored charge

QI W 0LL QI dy W LQIDsat
is calculated changing the integration variable
from y to QV

dy

sW

ID
nCox

QV dQV

resulting in

2 1 2
LI D
nCox
t
QVS
Q I W ( L L)
3 1
vsat
CMOS Analog Design Using All-Region MOSFET
Modeling

97

Source and drain charges including vsat

CMOS Analog Design Using All-Region MOSFET

Modeling

98

Capacitive coefficients including vsat - 1

Le g ms 1
2
1 2 qIS

C gs WLeCox

3
(1 ) 2 1 qIS 3nvsat 1 2
2

Le g md 1
2
2 2 qID

WLeCox

3
(1 ) 2 1 qID 3nvsat 1 2
2

C gd

2
Le gmg 1
n 1
Cox Cgso Cgdo

Cgb Cbg
2

n
3vsat 1

2
2
2
2
3

7
1

g
q

4
1

1
L
L
e
IS
ms
W e
Cds nCox

15
L 1 3 1 qIS 30 vsat L
1 3

2
3
2
qID
4
1 g md L e2 3 7 1
L
e 3
Csd nCox W

3
15
L 1
1 qID 30 vsat L
1 3

Cbs(d ) n 1 Cgs(d )

Cdg Cgd Csd Cds / n

CMOS Analog Design Using All-Region MOSFET
Modeling

99

Capacitive coefficients including vsat - 1

Normalized capacitances versus drain-source voltage

CMOS Analog Design Using All-Region MOSFET
Modeling

100

Gate-to-bulk capacitance with and

without the effect of velocity saturation

CMOS Analog Design Using All-Region MOSFET

Modeling

101