g a FUNCTIONS OF COMBINATIONAL LOGIC EN Troubleshooting Basic Adders EEE Digital system Application Parallel Binary Adders Ripple Carry versus Look-Ahead Carry Adders Comparators Distinguish between hal-adders and fll-adders Decoders Use fll- adders to implement mali parallel binary adders Sree Explain the differences between ripple catry and look-ahead Code Converters ‘carry parallel adders Restetetes (Dees soeson) Use the magnitude comparator to determine the relationship Demultiplexers ‘between two binary numbers ad use cascaded comparators to Parity Generators/Checkers handle the compari of lager number:"= Implement a basic binary decoder “= Ute BC-to-7-segment decoder in play nye “= Apply 2 decimal-to-BCD priority encoder in a simple keyboard pplication Convert fom binary to Gray code, and Gray code to binary by lusng logic devices © Apply multiplexers in data selection, multiplexed diplys, logic function generation, and simple communications systems © Use decoders a demultiplexers © Explain the meaning of party "Use paity generators and checker to detect bit errr in digital systems Implement a simple data communications stem Identify glitches, commen bugs in digital systems Cer Half-adder Encoder Fall-adder Priority encoder Cascading Multiplexer (MUX) Ripple carry Demultiplexer (DEMUX) Look-ahead cary Parity bit Decoder Glitch LT In this chapter, several types of combinational logic circuits are introduced including adders, comparators, decoders, cencoders, code converters, multiplexers (data selectors), demultiplexers, and party generators/checkers. Examples of fixed-function IC devices are included. SS FIXED-FUNCTION Locic DEVICES 7: 74X42 TAXXAT —74XX85, SS raxxi38 7900139 7401147 T4XX148 T4XX151 74XX154 TAXX157 TAXX280 74XX283 ZEA ‘The Digital System Application illustrates concepts from this chapter and deals with one portion of a traffic light control system. The system applications in Chapters 6, 7, and 8 focus (on various parts of the traffic light control system. Basically, this system controls the traffic light atthe intersection of 2 bury street and a lightly traveled side street. The system Includes a combinational logi section to which the topics Jn this chapter apply, a timing circuit section to which Chapter 7 applies, and a sequential logic section to which Chapter 8 applies Study aids for this chapter are available at hhtp:/[4venw prenhall.com/floyd 297298 = (BEM basic avvers FUNCTIONS OF COMBINATIONAL LOGIC. A alf-adder adds two bits and. produces 2 sum and a carry output. Equation 6-1 Adders are important in computers and also in other types of digital systems in which ‘numerical data are processed. An understanding of the basic adder operation is fundamental tothe study of digital systems. In this section, the half-adder and the full- adder are introduced. After completing this section, you should be able to = Describe the function of a half-adder ® Draw a half-adderlogie diagram = Deseribe the function of the full-adder = Draw a full-adder logie diagram using half-adders ® Implement a full-adder using AND-OR logic ‘The Half-Adder Recall the basic rules for binary addition as stated in Chapter 2. o+0=0 o+i=1 1+0= 1 1+1=10 ‘The operations are performed by a logic circuit called a half-adder. ‘The half-adder accepts two binary digits on its inputs and produces two binary digits on its outputs, a sum bit and a carry bit. Figure 6-1 A hualf-adder is represented by the logic symbol > FIGURE 6-1 Logic ymbol fora halF-adder. Open fa 7 rb sum bac: Vasu bmi de ste Input bits ‘Ouputs | cary Half-Adder Logic From the operation of the half-adder as stated in Table 6-1, expres- sions can be derived for the sum and the output carry as functions ofthe inputs. Notice that the output carry (C,.) isa L only when both A and B are Is; therefore, Cu Can be expressed as the AND of the input variables. Cou = AB Halfadder wuth table C= opty and B= ingt varies (operas)BASIC ADDERS = 299 [Now observe thatthe sum output (2) is 1 only if the input variables, A and B, are not equal, ‘The sum can therefore be expressed as the exclusive-OR of the input variables. E=Ae@B Equation 6-2 From Equations 6-1 and 6-2, the logic implementation required for the half-adder funetion can be developed. The output carry is produced with an AND gate with A and Bon the inputs, and the sum output is generated with an exclusive-OR gate, as shown in Figure 6-2. Remember that the exclusive-OR is implemented with AND gates, an OR gate, and inverters. < Figure 6-2 Halfadder logic diagram, “The Full-Adder “The second category of adder isthe full-adder. ‘Afull-adder has an input carry ‘The full-adder accepts two input bits and an input carry and generates asum Wile the halF adder does not ‘output and an output carry. ‘The basic difference between a full-adder and a half-adder is that the full-adder accepts an input carry. A logic symbol for a full-adder is shown in Figure 6-3, and the truth table in ‘Table 6-2 shows the operation of a full-adder. 4 Figure 6-3 toy | —J4 an Loge ymbol ora fll-adder Open A is | __ dy file FO6-03 to verity operation ee TABLE 6-2 | Folladdertruth table ‘G.= input cary, sometines desig as Cr Cua = ouput cay, sont desiged at CO A an B= apt varies (operas) Full-Adder Logic The full-adder must add the two input bits and the input carry. From the half-adder you know that the sum of the input bits A and B isthe exclusive-OR of those two300 = FUNCTIONS OF COMBINATIONAL LOGIC, Equation 6-3 (4) Logie raquied wo for the sum of thee bits (0) Complete os variables, A ® B. For the input carry (C,) to be added to the input bts, it must be exclusive ORed with A ® B, yielding the equation for the sum output ofthe full-adder, aenec, ‘This means that to implement the full-adder sum function, two 2-input exclusive-OR ‘gates can be used. The first must generate the term A @ B, and the second has as its inputs the output ofthe first XOR gate and the input cary, as illustrated in Figure 6-4(a). bya shaded rea) A FIGURE 6 Full-adder logic. Open file F06-04 to very operation. ‘The output carry is a 1 when both inputs to the first XOR gate are 1s or when both in- puts to the second XOR gate are Is. You can verify ths fact by studying Table 6-2. The out- put carry ofthe full-adder is therefore produced by the inputs A ANDed with Band A ® B ANDed with Ciy. These two terms are ORed, as expressed in Equation 6—4. This function is implemented and combined with the sum logic to form a complete full-adder circuit, as shown in Figure 6-4(b). Equation 6-4 Cu =AB+A®BC, [Notice in Figure 6-4) thee are two half-adders, connected as shown inthe block dia- ‘gram of Figure 6-5(a), with their output carries ORed, The logie symbol shown in Figure 6-5(b) will normally be used to represent the full-adder. Hater Hata = 3 72 eee 8 a sae = Rees a ale Sle (0) Arangeme of wo ballads o form fll (b) Full ader ogc symbol A FIGURE 6-5 Fall-adder implemented with hal-adder.PARALLEL BINARY ADDERS = 301 Bi z] ia ia 7 =|— =}— os ite ca Ce Co oe, oo o » © Solution (a) The input bits are A = 1, B =O, and Cy 1+0+0= 1 with no cary Therefore, Z = Land Cuy = 0. () The input bits eA = 1, B= 1 and C,, = 0. 1+1+0=Owith a carry of 1 Therefore, 2 = O and Coy = Le | A FIGURE 6-6 | (©) The input bits are A= 1, B =O, and Cy = 1 | 1+ 0+ 1=Owitha carry of | ‘Therefore, E = Oand Cys Related Problem” What are the full-adder outputs for A= 1, B= 1, and C= 1? "Answers are at the end ofthe chapter SECTION 6-1 ee a a oa Reve 1. Determine the sum (2) and the output cary (Cay) of halfadder for each sot of “Answers are at the end of the input bits: canta. (2) 01 (b) 00 (<) 10 (4) 11 2. Afulleadder has C,, = 1. What are the sum (2) and the output carry (Cixe) when A= and B= 17 (RB RMB paraLte BINARY ADDERS ‘Two or more full-adders are connected to form parallel binary adders, In this section, you will eam the basic operation of this type of adder and its associated input and ‘output Functions. After completing this section, you should be able to ‘= Use full-adders to implement a parallel binary adder ® Explain the addition process ina parallel binary adder # Use the truth table fora 4-bit parallel adder ® Apply two 74LS283s for the addition of two 4-bit numbers ® Expand the 4-bit adder to ‘accommodate 8-bit oF 16-bit addition302 = FUNCTIONS OF COMBINATIONAL LOGIC “Aan is perormed by Computers on two numbers ata time, called operands. The source operand isa umber that isto be added to an exiting number ‘called the destination operand, which i held in an ALU roger, such athe accumblator. The sum ‘ofthe two numbers then stored back inthe accumulator. Addition ‘performed on integer numbers “ox fleating-point numbers using ADD or FADD instructions respectively. > FIGURE 6-7 Block diagram of a basic 2-bit parallel adder using two full-adders, ‘Open file FD6-07 to verily operation [eames a Determine the sum generated by the 3-bit parallel adder in Figure 6-8 and show the ‘As you saw in Section 6-1, a single full-adder is capable of adding two 1-bit numbers and an input carry. To add binary numbers with more than one bit, you must use additional full-adders, When one binary number is added to another, each column generates a sum bit and a [ or O carry bit to the next column to the left, as illustrated here with 2-bit numbers. bit from right column In this case, the carry bit rom Sevond column becomes a sum bit ‘To add two binary numbers, a full-adder is required for cach bit in the numbers. So for 2-bit numbers, two adders are needed; for 4-bit numbers, Four adders are used; and So on, ‘The carry output of each adder is connected to the carry input of the next higher-order adder, as shown in Figure 6-7 for a 2-bit adder. Notice that ether a half-adder can be used forthe leas significant position or the carry input of a full-adder can be made 0 (grounded) ‘because there is no carry input tothe least significant bit position. A Gy rs en = aa I aise), 3 ase) In Figure 6-7 the least significant bits (LSB) of the two numbers are represented by A and B,, The next higher-order bits are represented by A, and B.. The three sum bits are), E,and Es. Notice that the output carry from the left-most full-adder becomes the most sig- nificant bit (MSB) in the sum, E5, intermediate carries when the binary numbers 101 and O11 are being added. > FIGURE 6PARALLEL BINARY ADDERS = 303 | Pe NET oe ey ee pre eet eset ree ane ‘What are the sum outputs when [11 and 101 are added by the 3-bit parallel adder? Four-Bit Parallel Adders A group of four bits is called a nibble. A basic 4it parallel adder is implemented with four full-adder stages as shown in Figure 6-9. Again, the LSBs (A, and B,) in each number be- ing added go into the right-most full-adder; the higher-order bits are applied as shown to the successively higher-order adders, with the MSBs (A, and B,) in each number being ap- plied to the left-most full-adder. The carry output of each adder is connected tothe carry in- putof the next higher-order adder as indicated, These are called internal carries [— [ane o1sp) ase) umber | — Input 6 at —! (2) Block diagram (©) Logic symbol A FIGURE 6-9 ‘Abit parallel adder. In keeping with most manufacturers’ data sheets, the input labeled Cy is the input carry to the least significant bit adder: C,, in the case of four bts, isthe output carry of the most significant bit adder; and , (LSB) through 3, (MSB) are the sum outputs. The logic sym- ‘bol is shown in Figure 6-9(b), Interms of the method used to handle carries in a parallel adder, there are two types: the ripple carry adder and the carry look-ahead adder. These are discussed in Section 6-3, “Truth Table for a 4-Bit Parallel Adder “Table 6-3 isthe truth table for a4bit adder. On some datasheets, truth tables may be called function tables or functional truth tables. The subscript represents the adder bits and can TABLE 6-3 Tht table foreach tage ofa bie parallel adder.304 = FUNCTIONS OF COMBINATIONAL LOGIC be 1,2,3,or4 forthe 4-bit adder. C, isthe cary from the previous adder Caries C), C and C; are generated intemally. Cp isan external carry input and C; isan output Example 63 illustrates how to use Table 6-3 \ EXAMPLE Use the 4-bit parallel adder truth table (Table 6-3) to find the sum and output carry for the addition ofthe following two 4-bit numbers if the input carry (C, 1) is 0: AdsAcA, = 1100 and ByBsBsB, = 1100 Solution For n = 1: A, = 0, B, =O, and C,_, = 0. From the Ist row of the table, %,=0 and c=0 | and C,.-, = 0, From the Ist row of the table, %=0 and C=0 Porn = 2:4; =0,By Form = 3:4; = 1, B= 1, and C,- = 0, From the 4th row of the table, %=0 and G=1 Form = 4: Ay = 1, By= 1, and C,- = 1. From the last row of the table, E=1 and C= 1 (C, becomes the output carry; the sum of 1100 and 1100 is 11000. Related Problem Use the truth table (Table 6-3) to find the result of adding the binary numbers 1011 and 1010. ‘An example of a 4-bit parallel adder that is available in IC form is the 741.8283. For the 74LS283, Voc is pin 16 and ground is pin 8, which isa standard configuration, The pin diagram ‘and logie symbol for this device are shown, with pin numbers in parentheses onthe logic sym- bol, in Figure 6-10. This device may be available in other TTL of CMOS families. Check the ‘Texas Instruments website at www ti.com or the TI CD-ROM accompanying this book. Four pede = ‘hoy : +) his To: 5 im (a) Pin diagram of 70.8283 () 7415283 logic symbolIC Data Sheet Characteristics Recall that logic gates have one specified propagation de~ lay time, fp, from an input to the output. For IC logic, there may be several different speci- fications for». The 4-bit parallel adder has the four ¢, specifications shown in Figure 6-11, which is part of a 74LS283 data sheet. PARALLEL BINARY ADDERS = 305 ae FIGURE 6-11 Symbol Parameter ‘Min [Typ | Max | Unit | Propagation delay characteristics for ‘mun | Propagation delay, Cp inptto 16 | 2 the 7415283, fra [ any output 5 | | ™ ‘nun | Propaenton delay, ny Aor B input is) | oF outputs ts | 2 ‘mun | Propagation doa, Cy npatto a | 7 fra | Cooupot | 2 |= ‘nun | Propeaton dy, any A or apa 7 | a fr | 1 Cyoutput vio|™ Adder Expansion ‘The 4-bit parallel adder can be expanded to handle the addition of two 8-bit numbers by using Adders can be expanded to two 4-bit adders. The carry input ofthe low-order adder (C,) is connected to ground because handle more bits by cascading. there is no carry into the least significant bit position, and the earry output of the low-order adder is connected to the carry input ofthe high-order adder, as shown in Figure 6-12(a). This | gs | o32es 3 2G pT esa was x z Gat Gaunt | (a) Cascading of two bit aero Forman Sit er a PEEUWEEDC ||| PEED aN aK |r T i | | (©) Cascading of four bit uders wo form a 16-bit adder A FIGURE 6-12 Examples of adder expansion,306 = FUNCTIONS OF COMBINATIONAL LOGIC [Pere 6-4 Solution process is known as cascading. Notice that, inthis case, the output camry is designated C, be- cause itis generated from the eighth bit position. The low-order adder is the one that add the Jower or less significant four bits in the numbers, and the high-order adder isthe one that adds the higher or more significant four bits in the 8-bit numbers. Similarly, four 4-bit adders can be cascaded to handle two 16-bit numbers as shown in Figure 6-12(b), Notice thatthe output carry is designated C,, because it is generated from the sixteenth bit position, Show how two 74LS283 adders can be connected to form an 8-bit parallel adder, Show output bits for the following 8-bit input numbers: AAAAAAAA, = LOLLO01 and B,B,B.BsB.BsB.B, }0011110 ‘Two 74LS283 4-bit parallel adders are used to implement the 8:bit adder. The only ‘connection between the two 741.S283s isthe carry output (pin 9) of the low-order adder to the carry input (pin 7) ofthe high-order adder, as shown in Figure 6-13. Pin 7 of the low-order adder is grounded (no carry input) ‘The sum of the two 8-bit numbers is | EXZZLLLLZ, = LOO. = F z Ay ait LEE Ay 0 * A, 0 * o at 1 A Z 2 Ee : x ?[oa7°% 8,0 2 a1 3 Fa | at 4 ef @|, py aI : mos [2 mi o o ° ck G « q igri aer Related Problem 3 ‘Two 7415283 adders connected a1 an 8-bt parallel adder (pin number are in paventhesei). Use 74L$283 adders to implement a 12-bit parallel adder. ‘An Application ‘An example of full-ndder and parallel adder application isa simple voting system that can be used to simultaneously provide the number of “yes” votes and the number of “no” votes. ‘This type of system can be used where a group of people are assembled and there is a need for immediately determining opinions (for or against), making decisions, or voting on cer- tain issues or other mattersPARALLEL BINARY ADDERS = 307 In its simplest form, the system includes a switch for “yes” or “no” selection at each po- sition inthe assembly and a digital display for the number of yes votes and one for the num ber of no votes. The basic system is shown in Figure 6-14 for a 6-position setup, but it can ‘be expanded to any number of positions with additional 6-position modules and additional parallel adder and display circuits, In Figure 6-14 each full-adder can produce the sum of up to three votes. The sum and. ‘output carry of each full-adder then goes t0 the two lower-order inputs of a parallel bi nary adder. The two higher-order inputs ofthe parallel adder are connected to ground (0) because there is never a ease where the binary input exceeds 0011 (decimal 3). For this Six-Poston Adder Medsle ep oe te 4 Lt si al ( | ®t ” 4 ofa Coa G Pale adder 1 Patkader2 1 Su Fi) cp Tscament seooder aeegeee ) Noo K ers ea) |g =| Pale adder 2 No lsic Resistors should te comme from the inputs of he al adders to grand. A FIGURE 6-16 ‘Avoting system using fll-adders and parallel binary adders308 = FUNCTIONS OF COMBINATIONAL LOGIC [fener 6-2 REVIEW basic 6-position system, the outputs of the parallel adder go to a BCD-to-7-segment de- ccoder that drives the 7-segment display. As mentioned, additional circuits must be in cluded when the system is expanded, ‘The resistors from the inputs of each full-adder to ground assure that each input is LOW when the switch is in the neutral position (CMOS logic is used). When a switch is moved to the “yes” or to the “no” position, a HIGH level (Vcc) is applied to the associ- ‘ated full-adder input. 1. Two 4-bit numbers (1101 and 1011) are applied to 24: ‘anys. Determine the sum (3) and the output erry. 2. How many 74LS283 adders would be required to add two binary numbers each representing decimal numbers up through 1000)? it parallel adder. The input (BBM ripple CARRY VERSUS LOOK-AHEAD CARRY ADDERS » URE 6 ‘Abit parallel ripple carry adder showing “wort-caie” cay propagation delay ‘As mentioned in the last section, parallel adders can be placed into two categories based on the way in which internal caries from stage to stage are handled. Those ‘categories are ripple carry and look-ahead carry. Externally, both types of adders are the Same in terms of inputs and outputs. The difference is the speed at which they ean add numbers. The look-ahead carry adder is much faster than the ripple carry adder. Afier completing this seetion, you should be able to ® Discuss the difference between a ripple carry adder and a look-ahead carry adder ' State the advantage of look-ahead carry addition ® Define carry generation and carry ‘propagation and explain the difference ® Develop look-ahead cary logic ® Explain why cascaded 7482835 exhibit both ripple carry and look-ahead carry properties ‘The Ripple Carry Adder A ripple carry adder is one in which the carry output of each full-adder is connected to the carry input ofthe next higher-order stage (a stage is one full-adder). The sum and the out- put carry of any stage cannot be produced until the input carry occurs; this causes a time delay in the addition process, as illustrated in Figure 6-15. The carry propagation delay for each full-adder is the time from the application of the input carry until the output carry 0€: ‘curs, assuming that the A and B inputs are already present.RIPPLE CARRY VERSUS LOOK-AHEAD CARRY ADDERS = 309 Full-adder 1 (FA1) cannot produce a potential output carry until an input carry is ap- plied. Full-adder 2 (FA2) cannot produce a potential output carry until full-adder 1 pro- duces an output carry. Full-adder 3 (FA3) cannot produce a potential output carry until an ‘output carry is produced by FAL followed by an output carry from FA2, and so on, As you can see in Figure 6-15, the input carry to the least significant stage has to ripple through all the adders before a final sum is produced. The cumulative delay through all the adder stages is a “worst-case” addition time. The total delay can vary, depending on the carry bit produced by each full-adder. If two numbers are added such that no carries (0) occur between stages, the addition time is simply the propagation time through a sin- gle full-adder from the application of the data bits on the inputs to the occurrence of a sum output. ‘The Look-Ahead Carry Adder “The speed with which an addition can be performed is limited by the time required for the carries to propagate, or ripple, through all the stages of a parallel adder. One method of speeding up the addition process by eliminating this ripple carry delay is called look- ahead earry addition, The look-ahead carry adder anticipates the output carry of each sage, and based on the inputs, produces the output carry by either carry generation or carry propagation. Carry generation occurs when an output cary is produced (generated) internally by the full-adder. A carry is generated only when both input bits are Is. The generated carry, C, is expressed as the AND function of the two input bits, A and B. C, = AB Carry propagation occurs when the input carry is rippled to become the output cary. ‘An input carry may be propagated by the full-adder when either or both of the input bits are 1s. The propagated carry, C, is expressed as the OR function of the input bits. GaAtB ‘The conditions for carry generation and carry propagation are illustrated in Figure 6-16. ‘The three arrowheads symbolize ripple (propagation). 11@ 01g «8 Ga| + BG on ou 1 1 1 Generated ———Propagatedcany?——_Propagated Propagied ay Gerented ry ary ty, ‘The output carry ofa full adder canbe expressed in terms of both the generated carry (C,) and the propagated carry (C,). The output carry (Cy) is | if the generated carry isa 1 OR it the propagated cary isa 1 AND the input carry (Cis a1. In other words, we get an output cary of | if ts generated by the full-adder (A = | AND B = 1) or if the adder propagates the input cary (A = 1 OR B= 1) AND C,, = 1. This relationship is expressed as Con = Cy + CCn Equation 6-5 Equation 6-6 GURE Illustration of conditions for eary generation and cary propagation. 6 Equation 6-7310 = FUNCTIONS OF COMBINATIONAL LOGIC Now let's see how this concept can be applied to a parallel adder, whose individual stages are shown in Figure 6-17 for a 4-bit example, For each full-adder, the output carry is dependent on the generated carry (C,), the propagated carry (C,), and its input carry (C,) ‘The C, and C, functions for each stage are immediately available as soon as the input bits A and B and the input carry to the LSB adder are applied because they are dependent only ‘on these bits. The input carry to each stage is the output carry ofthe previous stage. > FIGURE 6-17 (Canty generation and carry propagation in terms of the input bits to 3 4-bit adder. Fuladder 1 Based on this analysis, we can now develop expressions forthe output carry, Cyyy of each, full-adder stage for the 4-bit example, Fulhadder 1: Coat = Cy + GCs Fulladder 2: Gam Ge Coun = Ca + CpaCua Cat GalCu + GiGi) = Cat Cau Fulkadder 3: Cus = Cour Goas = Cpt Gana = Cpt Ga Cona = Cart GalCa+ Gay + GoCpiCut) Ca + Glyn + Sa Gay + GaGaC pCa Fuladder 4: Go Gs Coast = Coa + GyuCina = Cys + CpaCous Cot + CoalCya + CraCya + CraCnCyr + CCaCnCint) Coa + CuiCes + CuuaCua + CCG GCs Notice that in each ofthese expressions, the output carry foreach full-adder stage is de- Pendent only on the initial input earry (C,,), the C, and G, functions of that stage, and the C, and G, functions ofthe preceding stages. Since each of the C, and C, functions can be expressed in terms of the A and B inputs tothe full-adders, all the output carries are imme- diately available (except for gate delays), and you do not have to wait for a carry to ripple through all the stages before a final result is achieved. Thus, the look-ahead carry technique speeds up the addition process.COMPARATORS = 311 ‘The Cy equations are implemented with logic gates and connected tothe full-adders to create a 4-bit look-ahead carry adder, as shown in Figure 6-18, A FIGURE Loge diagram fora 4-stage look-ahead cary adder “Combination Look-Ahead and Ripple Carry Adders “The TALS283 4-bit adder that was introduced in Section 6-2 is a look-ahead carry adder. ‘When these adders are cascaded to expand their capability to handle binary numbers with ‘more than four bis, the output carry of one adder is connected to the input carry of the next. This creates a ripple carry condition between the 4-bit adders so that when two or more T4LS283s are cascaded, the resulting adder is actually a combination look-ahead and ripple carry adder. The look-ahead carry operation js internal to each MSI adder and the ripple carry feature comes into play when there is a carry out of one of the adders to the next one. [fener Co REVIEW 1. The input bits to a full-adder are A = 1 and B = 0. Determine C, and C,. 2. Determine the output carry of a full-adder when Cy, = 1, C, = 0, and C, [BEA comparators The basic function of a comparator is to compare the magnitudes of two binary ‘quantities to determine the relationship of those quantities. In its simplest Form, a ‘comparator circuit determines whether two numbers are equal, After completing this section, you should be able to 1 Use the exclusive-OR gate as a basic comparator ® Analyze the internal logic of a ‘magnitude comparator that has both equality and inequality outputs ® Apply the ‘74HCRS comparator to compare the magnitudes of two 4-bit numbers ® Cascade ‘TAHCS5s to expand a comparator to eight or more bits312 = FUNCTIONS OF COMBINATIONAL LOGIC ‘Equality As you learned in Chapter 3, the exclusive-OR gate can be used as a basic comparator be= cause its output is 1 if the two input bits are not equal and a O if the input bits are equal Figure 6-19 shows the exclusive-OR gate as a 2-bit comparator. o 1 ! 1 The np bits re not equ : > FIGURE 6-20 Logic diagram for equality comparion of two 2-bit number. ‘Open file FO6-20 to verify ‘operation. A comparator determines if two binary numbers are equal or unequal | [Resmecee 5 Y 0 The input is are equal a Figure Basic comparator operation, 19 In order to compat binary numbers containing two bits each, an additional exclusive- OR gate is necessary. The two least significant bits (LSBs) of the two numbers are com- pared by gate Gy, and the two most significant bits (MSBs) are compared by gate Gs, a8 shown in Figure 6-20. Ifthe two numbers are equal, their corresponding bis are the same, tnd the output of each exclusive-OR gate is a 0. If the corresponding sets of bits are not equal, a 1 occurs on that exclusive-OR gate output. = DD, =p! General format: Binary namber A -+AyAy In order to produce a single output indicating an equality or inequality of two numbers, ‘ovo inverters and an AND gate can be used, as shown in Figure 6-20. The output of each cexclusive-OR gate is inverted and applied to the AND gate input. When the two input bits for each exclusive-OR are equal, the corresponding bits of the numbers are equal, produc- ing a 1 on both inputs to the AND gate and thus a 1 on the output. When the two numbers are not equal, one or both sets of corresponding bits are unequal, and a 0 appears on at least ‘one input to the AND gate to produce a 0 on its output. Thus, the output of the AND gate indicates equality (1) or inequality (0) ofthe two numbers. Example 6-5 illustrates this operation for two specific cases. The exclusive-OR gate and inverter are replaced by an exclusive-NOR symbol. Perec te areata rete eer er pee sera OF apn over Bec ea ae (@) Wand 10 () Hand 10COMPARATORS = 313 A FIGURE 6-21 Solution (a) The output is 1 for inputs 10 and 10, as shown in Figure 6-21(a. | (b) The output is 0 for inputs 11 and 10, as shown in Figure 6-21(b). Related Problem Repeat the process for binary inputs of O1 and 10. [As you know from Chapter 3, the basic comparator can be expanded to any number of bits. The AND gate sets the condition that all corresponding bits ofthe two numbers must be equal if the two numbers themselves are equal. Es Ina computer, the cache 3 very fat intermediate memory between the central procesing ‘unit (CPU) and the slower main ‘memory. The CPU requests data by sending out ts acres (nique location) in memory, Part ofthis adres icalled 9 tag. The tag ‘adress comparator compares the tag from the CPU with the tag from the cache directory. Ifthe “Tnequality {In addition o the equality output, many IC comparators provide additional outputs that in- dicate which of the two binary numbers being compared isthe large. ‘That i, there isan ‘output that indicates when number 4 is greater than number B (A > B) and an output that indicates when number 4 is less than number B (A < B), as shown in the logic symbol for 14-bit comparator in Figure 6-22. < FIGURE 6-22 ‘comP SLISURE eens 4 —fo Logic ymbol fora 4-bit comparator | two agree, the addressed data is eae Sin Incanto lteady in the cache and is s A ase retrieved very quickly. If the tags je diagree, the data must be = retrieved from the main memory %)— 0 ata much lower ate, 8 p AB a,— a ‘To determine an inequality of binary numbers A and B, you first examine the highest- order bit in each number. The following conditions are possible: 1. IA, = 1 and B, = 0, number is greater than number B. 2. 1FAy=Oand B, = 1, number Ais less than number B. 3. IFA, = By then you must examine the next lower bit position for an inequality “These three operations are valid for each bit position in the numbers. The general pro- cedure used in a comparator is to check for an inequality ina bit position, starting with theae [Reser 6-6 Solution Related Problem FUNCTIONS OF COMBINATIONAL LOGIC highest-order bits (MSBs). When such an inequality is found, the relationship of the two ‘numbers is established, and any other inequalities in lower-order bit positions must be ig- nored because itis possible for an opposite indication to occur; the highest-order indica sion must take precedence. Determine the A = B, A> B, and A < B outputs for the input numbers shown on the comparator in Figure 6-23. > FIGURE 6-23, COMP 1 ace anB 1 ace "The number on the A inputs is 0110 and the number on the B inputs is 0011. The A> B output is HIGH and the other outputs are LOW. ‘What are the comparator outputs when AsAxA,Ap = 1001 and BuB,ByBy = 10107 » Figure 4 Pin diagram and logic symbol fo THHC8S 4-bit magnitude comparator (pin numbers are in ‘The 74HCSS is a comparator tha is also available in other IC families. The pin diagram and logic symbol are shown in Figure 6-24. Notice that this device has all the inputs and out- pls of the generalized comparator previously discussed and, in addition, has three cascad~ ing inputs: A < B, A = B, A> B, These inputs allow several comparators to be cascaded for ‘comparison of any aumber of bits greater than four. To expand the comparator, the A < B, parentheses). (a) Pin diagram ta) [5 cone the (2) ay] fA 5], 5 —Qhaee anat S cascasing | —@ GE inpus | “ey reve nee ol) un) ay | pe 8 Yec(16),GNDIS) (b) Logie symbatCOMPARATORS = 315 A= B, and A > B outputs of the lower-order comparator are connected fo the correspond- ing cascading inputs of the next higher-order comparator. The lowest-order comparator ‘must have a HIGH on the A = B input and LOWs on the A < B and A > B inputs. This de~ vvice may be available in other CMOS or TTL families. Check the Texas Instruments web- site at wwuati.com or the TI CD-ROM accompanying this book. [EXAMPLE I Use T4HC8S comparators to compare the magnitudes of two 8-bit mumbers, Show the ‘comparators with proper interconnections. Solution ‘Two TAHC8Ss are required to compare two 8-bit numbers, They are connected as shown in Figure 6-25 in a cascaded arrangement. > Figure 6-25 sp MBs ‘An B-bit mognitude comparator N ica joy | using Ho 74HCB5s A © A * A ADB A>e ADB ADB i. | sv A=B A=B \ + opus pace ace 1% 0 ae TaneKs Taos Related Problem Expand the circuit in Figure 6-25 to a 16-bit comparator. SECTION REVIEW 1. The binary numbers A = 1011 and B = 1010 are applied to the inputs of a T4HC8S. Determine the outputs. 2. The binary numbers A= 11001011 and B = 11010100 are applied to the 8-bit comparator in Figure 6-25. Determine the states of output pins 5, 6, and 7 on each 74HCBS. aes ‘Most CMOS devices contain protection circuitry to guard against damage from high static voltages or electric fields. However, precautions mutt be taken to avoid applications of any voltages higher than maximum rated voltages. For proper operation, input and out putvoltages should be between ground and Vec. Ao, remember that unuied inputs must always be connected to an appropriate logic level (ground or Vez). Unused outputs may be left open.316 = FUNCTIONS OF COMBINATIONAL LOGIC (B35 vecopers ry Ee ‘An intracton tell the computer what operation to perform. Instuetions are in machine code “(sand 03) and, in order forthe computer to cary out an instruction, the instruction must be decoded. Instruction decoding is one ofthe step in instruction Pipelining, which are 2 follows: Instruction i read from the memory (instruction fetch), “instruction is decoded, operands) is ote) read from memory (operand fetch), instruction is ‘executed, and result is written back to memory. Basically, Pipelining allows the next instruction to begin procesing before the erent one i “competed. | [Fxamece 6-8 Solution ‘A decoder isa digital circuit that detects the presence ofa specified combination of bits (code) om its inputs and indicates the presence ofthat code by a specified output level. In its general form, a decoder has 1 input lines to handle m bits and from one to 2” output lines to indicate the presence of one or more n-bit combinations. In this section, several ‘decoders are introduced. The basic principles can be extended to other types of Jecoxers. ‘After completing this section, you should be able to "= Define decoder Design a logic cireit to decode any combination of bits = Describe the T4HC154 binary-to-decimal decoder" Expand decoders to accommodate larger ‘numbers of bits ina code ® Describe the 74L.S47 BCD-to-7-segment decoder # Diseuss ‘zero suppression in 7-segment displays. = Apply decoders to specific applications |The Basic Binary Decoder Suppose you need to determine when a binary 1001 occurs on the inputs ofa digital circuit. [An AND gate cam be used asthe basic decoding element because it produces a HIGH out- putonly when al of its inputs are HIGH, Therefore, you must make sure that all of the in- pts tothe AND gate are HIGH when the binary number 1001 occurs; this ean be done by inverting the two middle bits (the Os), as shown in Figure 6-26 sa) ® & GURE 6-26 Decoding logic for the binary code 1001 with an actie-HIGH output. ‘The logic equation for the decoder of Figure 6-26(a) is developed as illustrated in Figure {6-26(b). You should verify that the output is O except when Ay = 1, A, = 0, Ay = 0, und Ay = L are applied to the inputs. Ay is the LSB and A, is the MSB. In the representation of a binary number or other weighted code in this book, the LSB is the right-most bit in 4 horizontal arrangement and the topmost bit in a vertical arrangement, unless specified otherwise Ifa NAND gate is used in place of the AND gate in Figure 6-26, a LOW output will in- dicate the presence of the proper binary code, which is 1001 in this case. See eee ee ‘The decoding function can be formed by complementing only the variables that | appear as 0 in the desired binary number, as follows: | X=AvivAy (1011)DECODERS = 317 ‘This function can be implemented by connecting the true (uncomplemented) variables Ap Aj, and As directly to the inputs of an AND gate, and inverting the variable A, before applying it to the AND gate input. The decoding logic is shown in Figure 6-27. » FIGURE 6-27 Decoding logic for producing 2 HIGH output when 1011 ison the Input Related Problem Develop the logic required to detect the binary code 10010 and produce an active- LOW output ‘The 4-Bit Decoder In order to decode all posible combinations of four bis, sixteen decowting gates are re wired (24 = 16) This type of decoder is commonly called ether a -line-10-f6-tine de Cader because there are four inputs and sixteen outputs or a I-of16 decoder because for any given code onthe inputs, one ofthe sixteen outputs is activated. A list ofthe sixten bi nary codes and ther corresponding decoding functions i given in Table 6-4. Tan aetive-LOW oatput is required fr each decoded number, the entre decoder can be {implemented with NAND gates and inverters, In order to decode each ofthe sixteen binary codes, sixteen NAND gates are required (AND gates can be used t0 produce active-HIGH outputs). TABLE 6-4 Decoding functions and tuth table fra Aine-to-16-line (1-016) decoder with sctve-LOW outputs. Pra NTS eng Eaten eee taco) oe318 = FUNCTIONS OF COMBINATIONAL LOGIC A logic symbol for a 4-line-to-I6-line (I-of-16) decoder with active-LOW outputs is shown in Figure 6-28. The BIN/DEC label indicates that a binary input makes the corre- sponding decimal output active. The input labels 8, 4, 2, and I represent the binary weights 227212, of the input > FIGURE 6 Logie bol for 3 4-line-to-16-line (1-0f-16) decoder. Open file FO6-28 {o verify operation, THE 74HC154.1-OF-16 DECODER BINDEC ‘The 74HC1S4 is a good example of an IC decoder. The logic symbol is shown in Figure Ge 6-29. There is an enable function (EN) provided on this device, which is implemented with eS a NOR gate used as a negative-AND. A LOW level on each chip select input, CS, and CS, < {s required in order to make the enable gate output (EN) HIGH, The enable gate output is > FIGURE 29 Din dagiam and logic symbol for the TAHCI54 1-of-16 decoder. e+ (0) in digg x a tole G24 few (©) Logie symbolDECODERS = 319 ‘connected to an input of each NAND gate in the decoder, soit must be HIGH for the NAND gates to be enabled. Ifthe enable gate is not activated by a LOW on both inputs, then all sixteen decoder outputs (1) will be HIGH regardless ofthe states ofthe four input variables, Ap. Ay. Aa, and As. This device may be available in other CMOS or TTL families. Check the ‘Texas Instruments website at wwwti.com or the TI CD-ROM accompanying this book. [Pxenoe 6 A certain application requires that a $-bit number be decoded. Use 74HC154 decoders to implement the logic. The binary number is represented by the format AyAyAsA Ap, Solution Since the 74HC154 can handle only four bits, two decoders must be used to decode five bits. The fifth bit, Ay, is connected to the chip seleet inputs, CS, and CS,, of one decoder, and A, is connected to the CS, and CS; inputs of the other decoder, as shown in Figure 6-30. When the decimal number is 15 or less, Ay = 0, the low-order decoder is enabled, and the high-order decoder is disabled. When the decimal number is greater than 15, Ay = 1 so Ay = 0, the high-order decoder is enabled, and the low- order decoder is disabled, > FIGURE 6-30 ‘A Scbit decoder wing MHCI54s, BINDES Law-onder High-onder ob—o ob— is 1 th— 7 | ap— is 3 sp— 4 4 5 5| ms 1 6 1 6 4, tt 2 ap—7 2 ap—2 4 4 sb— s fi sb— av 4—ts sb— 9 s ob— 2s "An Application Decoders are used in many types of applications. One example is in computers for input/output election as depicted in the general diagram of Figure 6-31. Computers must communicate with a variety of external devices called peripherals by sending and/or receiving data through what is known as input/output (VO) ports, These320. = FUNCTIONS OF COMBINATIONAL LOGIC » Figure A simplified computer /O port system with a port address decoder swith only four addres lines shown, InpuyOutpur pons Conair Paner « Data bus wo ev Keyboard i ——dav as Moir a 10 VO pore res These data = woraeip-tq [a SP? 1-4 Mi Port adres devoder external devices include printers, moclems, scanners, external disk drives, keyboard, video ‘monitors, and other computers. As indicated in Figure 6-31, a decoder is used to select the VO port as determined by the computer so that data can be sent or received from a specific external device, Each VO port has a number, called an address, which uniquely identifies it, When the ‘computer wants to communicate with a particular device, it issues the appropriate address code for the HO port to which that particular device is connected. This binary port address is decoded and the appropriate decoder output is activated to enable the VO port ‘As shown in Figure 6-31, binary data ae transferred within the computer on a data bus, which isa set of parallel lines. For example, an 8-bit bus consist of eight parallel lines that ccan carry one byte of data ata time. The data bus goes to all ofthe MO ports, but any data ‘coming in or going out will only pass through the port that is enabled by the port address decoder, ‘|The BCD-to-Decimal Decoder ‘The BCD-to-decimal decoder converts each BCD code (8421 code) into one of ten possi- ble decimal digit indications. It is frequently referred as a 4-line-to-10-lIne decoder ot & 1-0f-10 decoder ‘The method of implementation is the same as for the l-of-16 decoder previously dis- ‘cussed, except that only ten decoding gates are required because the BCD code represents only the ten decimal digits 0 through 9. A list of the ten BCD codes and their correspon: 12 decoding functions is given in Table 6-5. Each of these decoding functions is imple- mented with NAND gates to provide active-LOW outputs. If an active-HIGH output isDECODERS = 321 FIGURE 6-35 Pin dag nd log tl rte Mise) heb on? ogre a deo Wise a i sep 242 B Bie of) ¢ 2 Toda 7 wo (@) Pin diagram () Logie symbolDECODERS = 323 Lamp Test When a LOW is applied tothe ZT input and the Bi/RBO is HIGH, al ofthe 7 seg- ‘ments in the display are tumed on. Lamp tests used to verify that no segments are burned ou Zero Suppression Zero suppression isa feature used for multdigit displays to blank out Zero suppression results in unnecessary zeros. For example, in a 6-digit display the number 6.4 may be displayed as leading or tailing zeros in 2 (006.400 if the zeros are not blanked out. Blanking the zeros at the front of a number is number not showing on a called leading zero suppression and blanking the zeros atthe back of the number is called display. trailing zero suppression. Keep in mind that only nonessential zeros are blanked. With zero suppression, the number 030.080 will be displayed as 30.08 (the esse Zero suppression in the 74LS47 is accomplished using the RBI and BI/RBO functions. RBIs the ripple blanking input and RBO is the ripple blanking output on the T4LS47; these are used for zero suppression. BY i the blanking input that shares the same pin with f other words, the B//RBO pin can be used as an input or an output. When used as.a BI (blank ing input), all segment outputs are HIGH (nonactive) when BI is LOW, which overrides all other inputs. The BY function is not part of the zero suppression capability of the device. All of the segment outputs ofthe decoder are nonactive (HIGH) if a zero code (0000) is fn its BCD inputs and if its RBT is LOW. This causes the display to be blank and produces a LOW RBO. ‘The logic diagram in Figure 6-36(a) illustrates leading zero suppression for a whole ‘number. The highest-order digit position (left-most) is always blanked if a zero code is on 0 oo00 © 0000 0 00 1 loo i il | vp - 7aLS47 TALS? T4LS47 TALSA? Tn nro fii CL fit | oot Orit | 000 Ein LL LL 1 SL ae rin - cep TTT mm J Ty I) ay TI (6) Mustraton of walling zero suppression A FIGURE 6-36 Examples of zero suppression using the TALSA7 BCD to T-segment decoderldvver.324 = FUNCTIONS OF COMBINATIONAL LOGIC | fe ION. | Treview (EBS encovers its BCD inputs because the RBT of the most-significant decoder is made LOW by connect- ing ito ground, The RBO of each decoder is connected to the RB/ of the next lowest-order decoder so that all zeros tothe left ofthe fist nonzero digit are blanked. For example, in part (a) of the figure the two highestorder digit are zeros and therefore are blanked. The remaining two digits, 3 and 9 are displayed. ‘The logic diagram in Figure 6-36() illustrates trailing 2er0 suppression for a factional, number. The lowest-order digit (right-most) i always blanked if zero code i on its BCD inputs because the RAT is connected to ground. The RBO of each decoder is connected to the RBI ofthe next highest-order decoder so that all zeros tothe right ofthe first nonzero digit are blanked. In part (by of the figure, the two lowest-order digits are zeros and there- fore are blanked. The remaining two digits, Sand 7 are displayed, To combine both leading additional and trailing zero suppression in one display and to have decimal point capabil logic is required. 1. A Hline-to-8-line decoder can be used for octal-to-decimal decoding. When a binary 101 is on the inputs, which output line is activated? 2. How many 74HC154 1-of-16 decoders are necesary to decode a 6-bit binary number? 3. Would you select a decoder/drver with active-HIGH or active-LOW outputs to drive a common-cathode 7-segment LED display? ‘An encoder is a combinational logic circuit that essentially performs a “reverse” decoder function. An encoder accepts an active level on one of its inputs representing a digit, such as a decimal or octal digit, and converts it to a coded output, such as BCD or binary. Encoders can also be devised to encode various symbols and alphabetic characters. The process of converting from familiar symbols or numbers to a coded format is called encoding. After completing this section, you should be able to ® Determine the logic for a decimal encoder ® Explain the purpose of the priority feature in encoders = Describe the T4HC147 decimal-to-BCD priority encoder ® Describe the 74L$148 octal-to-binary priority encoder ® Expand an encoder "= Apply the encoder to a specific application ‘The Decimal-to-BCD Encoder ‘This type of encoder has ten inputs—one for each decimal digit—and four outputs corre- sponding tothe BCD code, as shown in Figure 6-37. This isa basic 10-line-1o-4-line encoder, ‘The BCD (8421) code is listed in Table 6-6. From this table you can determine the re lationship between each BCD bit and the decimal digits in order to analyze the logic, For instance, the most significant bit of the BCD code, Ay, is always a I for decimal digit 8 or 9. An OR expression for bit A; in terms of the decimal digits can therefore be written as As=8+9Figure 6-37 Loge symbol for» decimal-to-BCD encoder. DECTHCD Decimat | — ‘amt } —— Ej\s Bit Ay is always a 1 for decimal digit 4, 5, 6 or 7 and can be expressed as an OR function as follows: Ay +546+7 Bit A is always a | for decimal digit 2,3, 6, or 7 and can be expressed as Ay=2434647 Finally, 4p is always a for decimal digit 3, 5, 7,09. The expression for Ay is Age t3454749 [Now let’s implement the logic circuitry required for encoding each decimal digit to a BCD code by using the logic expressions just developed. Itis simply a matter of ORing the appropriate decimal digit input lines to form each BCD output. The basic encoder logic re- sulting from these expressions is shown in Figure 6-38. IGURE. 38 fo SD) Basi lie diagram of decimalto- BCD encoder. A O-digt input it not 4 needed becaure the BCD outputs are all LOW when there are no i HIGH inputs. Ay (MSB) ENCODERS 325 puts (recall that the octal digits are O through 7) to a3-bit binary code. To enable the device, i < the £7 (enable input) must be LOW. It also has the EO (enable output) and GS output for >] expansion purposes. The EO is LOW when the Bis LOW and none ofthe inputs (0 through 7) is active. GS is LOW when Elis LOW and any of the inputs is active. This device may be available in other TTL or CMOS families. Check the Texas Instruments website at ‘wwwati.com or the TICD-ROM accompanying this book.ENCODERS = 327 Yee pli LL Lee a | Logie symbol forthe TALSTAB feo Brlineto-3eline encoder. oo | RN —fda £0 an J, os an, fi ad) 4 ods F od, ods od wd; ® exp ‘The 74LS148 can be expanded to a 16-line-to-4-line encoder by connecting the EO of the higher-order encoder to the EI of the lower-order encoder and negative-ORing the cor- responding binary outputs as shown in Figure 6-41. The £0 is used as the fourth and most- significant bit. This particular configuration produces active-HIGH outputs for the 4-bit binary number LU UL ol sees Binary ops EXAMPLE 6-11) IF LOW Levels appear on pins, 1, 4, and 13 of the 74HC147 shown in Figure 6-39, indicate the state of the four outputs. All other inputs are HIGH. Solution Pin 4s the highest-order decimal digit input having a LOW level and represents decimal 7. Therefore, the output levels indicate the BCD eode for decimal 7 where Aa is the LSB and A, is the MSB, Output Ay is LOW, A, is LOW, A, is LOW, and Ais HIGH. Related Problem What are the outputs of the 74HC147 if all ts inputs are LOW? If all its inputs are HIGH?328 = FUNCTIONS OF COMBINATIONAL LOGIC > Figure 6-42 ‘A simplified keyboard encoder. | fe ION 6-6 REVIEW BBs Ap ‘Acassic application enample isa Keyboard encode: The tn decimal digits on the keyboard ofa computer, fr example, mst be encoded for processing by the 1pie circuitry. When ne ofthe Kes is pressed the decimal gts encoded to te coetponding BCD code Figure 6-42 shows a simple keyboard encoder arrangement wing 74HC147 priority en- codes They Keys ar represent by en pusbbutonswlches, eck witha pll-ap reser to +0 The plop resistor ensues hatte ies HIGH wena ky is not dcpresied. When ‘key is depresed the ln s connected to ground, and u LOW i applied tothe corespon- Ging encoder inp. The neo ley is wot connected because the BCD cuit represen tro reste ee fw eee "The BCD complement ouput the encoder goes int a sorage device, and each su cessive BCD code is tore unl te etre numer has bon eed. Mctods of sorag BCD numbers and binary daa are covered in later chapter. HPRIBCD } RCD complement TACIT {AIL BCD complement lines tre HIGH idating 30, No enending neces. 1. Suppose the HIGH levels are applied tothe 2 input and the 9 input ofthe circuit in Figure 6-38. (a) What are the states of the output lines? (b) Does this representa valid BCD code? (€) Whats the estrction on the encoder logic in Figure 6-38? 2. (a) Whatis the AA, Ardy output when LOWs are appliod to pins 1 and 5 ofthe TAHCHAT in Figure 6-39? (b) What does this output represent?CODE CONVERTERS = 329 (BEM cone converters In this section, we will examine some methods of using combinational logic circuits to ‘convert from one code to another. After completing this section, you should be able t0 ‘= Explain the process for converting BCD to binary = Use exclusive-OR gates for conversions between binary and Gray codes ‘BCD-to- (One method of BCD-to-binary code conversion uses adder circuits, The basic conversion process is as follows: inary Conversion 1, The value, or weight, ofeach bitin the BCD number is represented by a binary number, 2. Allof the binary representations of the weights of bts that are Is in the BCD ‘number are added. 3 ‘The result of this addition isthe binary equivalent of the BCD number A more concise statement of this operation is ‘The binary numbers representing the weights of the BCD bits are summed to produce the total binary number. Let’s examine an 8-bit BCD code (one that represents a 2-digit decimal number) to un- derstand the relationship between BCD and binary. For instance, you already know thatthe decimal number 87 can be expressed in BCD as 1000 111 cr ‘The left-most 4-bit group represents 80, and the right-most 4-bit group represents 7. That is, the lefi-most group has a weight of 10, and the right-most group has a weight of 1. Within each group, the binary weight of each bit is us Follows: ‘Tens Digit, Units Di Weigh: 80 40 2 10 8 4 2 1 Bitdesignation: By By By By Ay Aa Ay Ag ‘The binary equivalent of each BCD bit isa binary number representing the weight of that bit within the total BCD number. This representation is given in Table 6-7. FIGURE 6-43, Binary Gay + Fourbit binay-to-Gray convenion By) — ee logic. Open file FO6-43 to verify ‘operation % i -D.,MULTIPLEXERS (DATA SELECTORS) = 331 Gny Binary FIGURE 4% y, «spy Fourbie Gray-to-binary convenson loge. Open file 6-44 to verify ‘operation, o 3 fue I EXAMPLE 6-13 | (b) Convert the Gray code 1011 to binary with exclusive-OR gates, 5 sB) (@) Convert the binary number 0101 to Gray code with exclusive-OR gates. Solution (a) 0101, is O111 Gray. See Figure 6-45(a). (b) 1011 Gray is 1101,. See Figure 6-45(b). > Figure 6-45 © © Related Problem How many exclusive-OR gates are required to convert §-bit binary to Gray? [Free REVERE 1. Convert the BCD number 10000101 to binary. 2. Draw the logic diagram for converting an 8-bit binary number to Gray code, (223MM mucticexers (DATA SELECTORS) A multiplexer (MUX) isa device that allows digital information from several sources to be routed onto a single line for transmission over that line to a common destination. ‘The basic multiplexer has several data-input lines and a single output line. I also has data-select inputs, which permit digital data on any one of the inputs to be switched 0 the output ine. Multiplexers are also known as data selectors, After completing this section, you should be able to «= Explain the basic operation of a multiplexer ® Describe the 748151 and the ‘74HC157 multiplexers ® Expand a multiplexer to handle more data inputs ® Use the ‘multiplexer asa logic function generator332 = In a multiplexer, data goes from several lines to one line. > TABLE 6-1 Data selection fora T-of- 4-multiplexer ‘A bus 20 internal pathway along ‘which electrical signals are sent from one part ofa computer to another In computer networks, 2 shared bus sone that ie connected to all the microprocesors in the system in order to exchange data A shared ‘bus may contain memory and Inputloutput devices that can be cessed by all the microprocesors inthe system. Acces to the shared bus is controlled by a bus arbiter (a multiplexer ofsorts) that allows | only one microprocesior at» time t0.use the system's shared bus en FUNCTIONS OF COMBINATIONAL LOGIC A logic symbol for a 4-input multiplexer (MUX) is shown in Figure 646, Notice that there are two data-select lines because with two select bits, any one of the four data-input lines can be selected. » Figure ee et MX Logic ymbol for a I-oF 4 data ee, selector/multplexer. sete | 5; —]1 3 y Paw ata } 2) —}1 ces Pon a \o—s In Figure 6-46, a -bit code on the data-select(S) inputs will allow the data on the se- {ected data input to passthrough tothe data output. Ifa binary 0 (S, = 0 and Sy = 0) is ap- plied to the data-select lines, the data on input D) appear on the data-output line, Ifa binary 1 (S, = Oand S, = 1) is applied tothe data-seect lines, the data on input Dy appear on the data output. Ifa binary 2 (S, = 1 and S) = 0) is applied, the data on D, appear on the out- pt. Ifa binary 3 (S, = 1 and S) = 1) is applied, the data on D, are switched to the output line. A summary of this operation is given in Table 6-8. 0. Do 0 1 D, i 70 Ds 1 1 Dy Now let's look at the logic cireuitry required to perform this multiplexing operation, The data output is equal to the state ofthe selected data input, You can therefore, derive a logic ‘expression for the output in terms of the data input and the select inputs ‘The data output is equal to Dy only iS, = Oand S, DSSy ‘The data output is equal o D, only if = Oand Sy DSSy ‘The data output is equal to D; only if, = 1 and Sy DSS, ‘The data output is equal to D, only if, = 1 and Sy DSS ‘When these terms are ORed, the total expression for the data output is ¥ = DySiSp + DiS,Sy + D:S,5p + D:SiSy The implementation of this equation requires four 3-input AND gates, a4-input OR gate, and to inverters to generate the complements of S, and Sy, as shown in Figure 6-47. Be- cause data can be selected from any one ofthe input lines, this circuit is also referred to as 2 data selector.MULTIPLEXERS (DATA SELECTORS) = 333 FIGURE 6-47 Logie diagram fora input ‘multiplexer. Open fle 6-47 to vetfy operation. a I EXAMPLE 6: ‘The data-input and data-select waveforms in Figure 6-48(a) are applied to the ‘multiplexer in Figure 6-47. Determine the output waveform in relation tothe inputs. > FiguRE 6-48 oy Solution The binary state of the data-select inputs during each interval determines which data input is selected. Notice that the data-select inputs go through a repetitive binary sequence 00, 01, 10, 11,00, 01, 10, 11, and so on, The resulting output waveform is shown in Figure 6-48(b) Related Problem Construct a timing diagram showing all inputs and the output ifthe Sy and 5, ‘waveforms in Figure 6-48 are interchanged. ‘The 74HC1S7, as well as its LS version, consists of four separate 2-input mu Each of the four multiplexers shares a common dats-select line and a common Enable, Be- cause there are only two inputs to be selected in each multiplexer, a single data-select in- putis sufficient334. = FUNCTIONS OF COMBINATIONAL LOGIC > FIGURE 6-49 Pin i selector/multiplexer. sn and loge symbol forthe 74H1C157 quadruple 2-input data w A LOW on the Enable input allows the selected input data to pass through to the output AHIGH on the Enable input prevents data from going through to the output; that is, itd ables the multiplexers. This device may be available in other CMOS or TTL families. Check the Texas Instruments website at wwwi.com or the TL CD-ROM accompanying this book The ANSI/IEEE Logic Symbol The pin diagram for the 74HC1S7 is shown in Figure 6-49(a). The ANSVIEEE logic symbol for the 74HC1S7 is shown in Figure 6-49(b). No- tice that the four multiplexers are indicated by the partitioned outline and that the inputs common to all four multiplexers are indicated as inputs to the notched block at the top, which is called the common control block. All labels within the upper MUX block apply to the other blocks below it pata sececr (7M Vc Bae el Dat ines 1B pia) 4a Oye v fa) a8 ot 24 fray | 28 3A un] sy rG ot sy 0| 7 2 ay ono [x] aay ty (0) Pinna (2) Logic ymbol Notice the | and I labels in the MUX blocks and the GI label in the common control block. These labels are an example of the dependency notation system specified in the ANSI/IEEE Standard 91-1984, In this case GI indicates an AND relationship between the data-select input and the data inputs with { or I labels. (The 1 means that the AND relationship applies to the complement of the GI input.) In other words, when the data- select input is HIGH, the B inputs of the multiplexers are selected: and when the data- select input is LOW, the A inputs are selected. A “G” is always used to denote AND de- pendency. Other aspects of dependency notation are introduced as appropriate through- ‘out the book, The 74LS151 has eight data inputs (Dy-D,) and, therefore, three data-select or addres put ines (S;~S:). Three bits are required to select any one of the eight data inputs (2° = 8). A LOW on the Enable input allows the selected input data to pass through to the output. Notice thatthe data output and its complement are both available. Te pin diagram is shown in Figure 6-50(a), and the ANSV/IEEE logic symbol is shown in part (b). In this case there is no need for a common control block on the logic symbol because there is only one mul- Liplexer to be controlled, not four as in the 74HC157. The Gi label within the logic symbol indicates the AND relationship between the data-select inputs and each ofthe data inputs 0 through 7. This device may be available in other TTL or CMOS families. Check the Texas Instruments website at www.ti.com or the TI CD-ROM accompanying this book.MULTIPLEXERS (DATA SELECTORS) = 335 Pin diagram and logic symbol fr the 74LS151 B-input data selector multiplexer. () Logie symbol | EXAMPLE 6-15 Use 74LS15Is and any other logie necessary to multiplex 16 data lines onto a single | data-output line, implementation of this system is shown in Figure 6-51. Four bits are required 10 | select one of 16 data inputs (2* = 16). In his application the Enable input i used as the most significant data-sclect bit. When the MSB in the data-select code is LOW, the left 74L.S151 is enabled, and one ofthe data inputs (Dy through D;) is selected by the other tree dataselect bis. When the data-select MSB is HIGH, the right 74LS151 is ‘enabled, and one ofthe data inputs (D, through D,.) is selected. The selected input ata are then passed through to the negative-OR gate and onto the single output ine > FIGURE 6-51 ‘A esnput nlp = " = 16 74HC04 i 5, Gt 4 2. : 1 2 ona a ee ots ey Related Problem Determine the codes on the select inputs required to select each of the following data Ez Inputs: Dy, Dy, Dy and Das336 = FUNCTIONS OF COMBINATIONAL LOGIC > FIGURE 6-52 Simplified 7segment diplay multiplexing loge ‘Applications A 7-Segment Display Multiplexer Figure 6-52 shows a simplified method of multiplex ing BCD numbers to « 7-segment display. In this example, 2-digit numbers are displayed on the 7-segment readout by the use of a single BCD-to-7-sezment decoder. This basic ‘method of display multiplexing can be extended to displays with any numberof digits Z pf a as A wr CE i =f : S es = Fe | = S [le oe | wort, mame] py | LOW enables LSD_ I / = pe “*Additional buffer drive mb— | ‘ireuitry may be required fe a = yuisis9 The basic operation is as follows. Two BCD digits (AyA-A,Ap and BsBsB,By) are ap- plied to the multiplexer inputs. A square wave is applied to the data-select line, and when itis LOW, the A bits (A,4s4 4a) are passed through to the inputs of the 74LS47 BCD-to- 7-segment decoder. The LOW on the data-select also puts a LOW on the A, input of the T4LS139 2-line-to-4-line decoder, thus activating its 0 output and enabling the A-digit display by effectively connecting its common terminal to ground. The A digit is now onMULTIPLEXERS (DATA SELECTORS) When the data-select line goes HIGH, the B bits (ByB:BB,) are passed through to the inputs of the BCD-to-7-segment decoder. Also, the 74L.S139 decoder’s 1 output is acti- vated, thus enabling the B-digit display, The B digit is now on and the A digit is off The cy- cle repeats atthe frequency of the data-select square wave. This frequeney must be high enough (about 30 Hz) to prevent visual flicker as the digit displays are multiplexed. A Logic Function Generator useful application ofthe data selector/multiplexeris inthe ‘generation of combinational logic functions in sum-of-produets form. When used in this ‘way, the device can replace discrete gates, ean often greatly reduce the number of ICs, and ccan make design changes much easier. ‘To illustrate, a T4LS151 8-input data selector/multiplexer can be used to implement any specified 3-variable logic function if the variables are connected to the dats-select inputs and each data input is set to the logic level required in the truth table for that function. For ‘example, if the function is a 1 when the variable combination is Ay44y, the 2 input (se- lected by 010) is connected to a HIGH. This HIGH is passed through to the output when this particular combination of variables occurs on the data-select lines. An example will help clarify this application [eam LE 6-16 Implement the logic function specified in Table 6-9 by using a 74LS151 8-input data selector/multiplexer, Compare this method with a diserete logic gate implementation, TABLE Solution Notice from the truth table that Y isa 1 for the following input variable combinations: 001, 011, 101, and 110, For all other combinations, ¥ is 0. For this function to be implemented with the data selector, the data input s each of the above-mentioned combinations must be connected to a HIGH (5 V), All the other data inputs must be connected to a LOW (ground), as shown in Figure 6-53. ‘The implementation of this function with logic gates would require four 3-input AND gates, one 4-input OR gate, and three inverters unless the expression can be simplified 337338 "FUNCTIONS OF COMBINATIONAL LOGIC | Data selector/ multiplexer [eemereeteattgs | clon sot > FIGURE 6-53 Related Problem EXAMPLE 6-17 Solution MO 4 — tmp {4 | Lge la—}a o asv 1 Er tact ; Ly = Asdyay + ApAydy + Arde +AsA i ho A S | 6 on =H fn 7asish implemen the following expression AyA\Ay + Ard Ay + Ardy Example 6-16 illustrated how the 8-input data selector can be used as a logic function gen: erator for three variables. Actually, this device can be also used as a 4-variable logic function ‘generator by the utilization of one ofthe bits (44) in conjunction with the data inputs. ‘A 4variable truth table has sixteen combinations of input variables. When an 8-bit data selector is used, each input is selected twice: the first time when A, is O and the second time ‘when 4p is 1. With this in mind, the following rules can be applied (Y is the output, and Ay is the least significant bit): |. IFY = O both times a given data inp is selected by a certain combination ofthe input variables, Ay4sA, connect that data input to ground (0) 2. IF Y= 1 both times a given data input i selected by a certain combination of the input variables, Ay4sA, connect the data input to +V (1). 3. If Yis different the two times a given data input is selected by a certain ‘combination of the input variables, A;A2A,, and if Y= Ay, connect that data input toAy, IF is different the two times a given data input is sclected by a certain combination of the input variables, AAs, and if Y=Ay, connect that data input to Ay 4 Implement the logic function in Table 6-10 by using a 74LS151 8-input data selector/multiplexer. Compare this method with discrete logic gate implementation. he dats ipl Assy. nthe io fe ale os = ant Y= Inthe second rm, Ay ga 3000, Y= AT ta ‘connected to the 0 input. Inthe third row of the table, ‘AsAxA, = 001 and | ‘Also, inthe fourth row, when AyAsA, again is 001, Y=Ay. Thus, Ay is inverted and> FIGURE 6-54 MULTIPLEXERS (DATA SELECTORS) = 339 ‘connected to the | input. This analysis is continued until each input is properly connected according to the specified rules. The implementation is shown in Figure 6-54 Data slectorimultiplexer connected a 3 4varible logic function generator. Related Problem 0 q [= AsAsdydy + daa Ay + Aya ae E + Auda + Aydatido ¢ Avda dy ¢ l + Assi Asso + AAA b + AvdaAiy 6 Os TaIsist IFimplemented with logic gates, the function would require as many as ten 4-input AND gates, one 10-input OR gate, and four inverters, although possible simplification ‘would reduce this requirement In Table 6-10, if ¥ = 0 when the inputs are all zeros and is alternately & 1 and a 0 for the remaining rows in the table, use a 74LS151 to implement the resulting logic function,340 = FUNCTIONS OF COMBINATIONAL LOGIC a REVIEW 1. In Figure 6-47, Dy = 1, D, = 0, Dp = 1, D = output? 2, Identity each device. (2) 7415157 (b) 7415151 3. ATALS151 has alternating LOW and HIGH level on its data inputs beginning with ‘Dy = 0. The data-selct lines are sequenced through a binary count (000, 001, 010, ‘and s0 on) at a fequency of 1 kHz. The enable input is LOW. Describe the data ‘output waveform, 4. Briefly describe the purpose of each of the following devices in Figure 6-52: (2) 7415157 (b) 741847 (¢) 7415139 (29M vemuttiptexers Ina demultiplexer, data goes from one line to several lines. > FIGURE 6-55 A V-line-to-4-tine demultiplexer A demultiplexer (DEMUX) basically reverses the multiplexing function. It takes, toa given number of output lines. reason, the demultiplexer is also known as a data distributor, As you will Tearn, decoders can also be used as demultiplexers. Afr completing this section, you should be able to '= Explain the basic operation of a demultiplexer ® Describe how the 74HC154 4-Tine-to-16-Line decoder ean be used as a demultiplexer = Develop the timing diagram for a demultiplexer with specified data and data selection inputs Figure 6-55 shows a I-line-to-4-line demultiplexer (DEMUX) circuit, The data input line goes o all of the AND gates. The two data-select lines enable only one gate ata time, and the data appearing on the data-input line will pass through the selected gate to the as- sociated data-output line, sn DH :put waveform (Data in) and data-select inputs (Sy and $}) are shown in Figure 6-56. Determine the data-ourput waveforms on D, through D, for the ‘demultiplexer in Figure 6-55.DEMULTIPLEXERS = 341 > FIGURE 6-56 Solution Notice that the select lines go through a binary sequence so that each successive input bit is routed to Ds, Dj, D>, and Ds in sequence, as shown by the output waveforms in Figure 6-56, Related Problem Develop the timing diagram for the demultiplexer if the 5, and S, waveforms are both inverted. TEaAHGI 54 DEMULTIBLEXER We have already discussed the 74HC154 decoder in its application as a 4-ine-to-16-Line f decoder (Section 6-5). This device and other decoders can also be used in demultiplexing applications. The logic symbol for this device when used as a demultiplexer is shown in Figure 6-57. In demultiplexer applications, the input lines are used asthe data-select lines. One ofthe chip select inputs is used as the data-input lin, with the other chip select input held LOW to enable the internal negative-AND gate at the bottom of the diagram. This de- vice may be available in other CMOS or TTL families, Check the Texas Instruments web- site at www.ti.com or the TI CD-ROM accompanying this book.

FiguRE 6. ; @) Summing ofevo bes (6) Summing of fou itsPARITY GENERATORS/CHECKERS = 343 ‘The logic symbol and function table for a 741S280 are shown in Figure 6-59. This partic- ular device can be used to check for odd or even parity on a 9-bit code (cight data bits and ‘one parity bit) oritcan be used to generate a parity bit for a binary code with up to nine bits, ‘The inputs are A through J: when there is an even number of 1s on the inputs, the E Even output is HIGH and the ¥ Odd output is LOW. This device may be available in other TTL ‘or CMOS families. Check the Texas Instruments website at www.ti.com or the TI CD-ROM accompanying this book. |, a0}? ao |e pu | 2245 oy ‘ep } Ee oO. Fe Input e eee 4 1 (4) Trains loge symbol (6) Funetion able A FIGURE 6-59 ‘The 7415280 9-bit pay generatorlchecker. Parity Checker When this device is used as an even parity checker, the number of input bits should always be even; and when a parity error occurs, the 2 Even output goes LOW and the © Odd output goes HIGH, When itis used! as an odd parity checker, the number of Input bits should always bé odd; and when a parity error occurs, the Z Odd output goes LOW and the © Even output goes HIGH. Parity Generator If this device is used as an even parity generator, the parity bit is taken atthe © Odd output because this output is a0 if there is an even number of input bts and it is. Lif there isan odd number. When used as an odd parity generator, the parity bit is taken atthe © Even output because it is a 0 when the number of inputs bits is odd A Data Transmission System with Error Detection A simplified data transmission system is shown in Figure 6-60 to illustrate an application of parity generators/checkers, as well as multiplexers and demultiplexers, and to illustrate the need for data storage in some applications. In this application, digital data from seven sources are multiplexed onto a single line for ‘transmission to a distant point. The seven data bits (Dj through D,) ate applied to the mul- tiplexer data inputs and, atthe same time, to the even parity generator inputs. The © Odd ‘output of the party generator is used as the even parity bit. This bit is 0 if the number of Is on the inputs A through Fis even and is 1 if the number of 1s on A through 1 is odd. This bit is D, ofthe transmiteed code. ‘The data-select inputs are repeatedly cycled through a binary sequence, and each data bit, beginning with Dy, is serially passed through and onto the transmission line (¥). In344 = FUNCTIONS OF COMBINATIONAL LOGIC Dy, Ee |The Pentium microprocesor perform intemal patty checks a+ wells pity checks ofthe external data and aes use, ln read ‘operation the external stem can tranfer the party information together withthe data bytes. The Pentism checks whether the resting party i even and sends out the comesponding signal: When it tend out an addres code, the Pentium doesnot perform an address, arty check, butt does generate an | even parity it for the adres Fou ondctor ansmision ine TALSI38 7aISiSi ven parity bit(D;) Eve parity i Storage | EVEN parity EVEN pasty crertor checker C5280) ‘Storage devies are itoduced in (ALs280) (Chup 9 and used ia eter ae chapters A-FIGURE 6-60 in Simplified data transmision stem with eror detection, this example, the transmission line consists of four conductors: one carries the serial data and three cary the timing signals (data selects). There are more sophisticated ways of sending the timing information, but we are using this direct method to illustrate a basic principle. At the demultiplexer end of the system, the data-select signals and the serial data stream are applied tothe demultiplexer. The data bts are distributed by the demultiplexer ‘nto the output lines in the order in which they occurred on the multiplexer inputs. That is, Dp comes out on the Dp output, D; comes out on the D; output, and o on. The parity bit comes out onthe D, output. These eight bts are temporarily stored and applied to the even party checker. Not all of the bits are present on the party checker inputs until the parity bit D; comes out and is stored. At this time, the error gate is enabled by the data- select code 111. IF the party is correct, a 0 appears on the ¥ Even output, keeping the Error output at 0. If the party is incorrect, all 1 appear on the error gate inpus, and a {on the Error output resultsTROUBLESHOOTING = 345 ‘This particular application has demonstrated the need for data storage so that you will be better able to appreciate the usefulness ofthe storage devices that will be introduced in Chapter 7 and used in other later chapters. ‘The timing diagram in Figure 6-61 illustrates a specific case in which two 8-bit words are transmitted, one with correet parity and one with an error, O12 34567 s67 sricune 6-61 s, ; Example of dla taramision with a 1 ' and without enor er the stm n ‘Seige ie Figure 6-60. sii t Fro ti hres itaataetag Fim ets FLA. HH! Gemeeninen Wap 440i )s405 stout ost tosos oot, SECTION 6-10 ss | REVIEW 1. Add an even parity bit to each of the following codes: | (a) 110100 (b) 01100011 2. Add an odd parity bit to each of the following codes: | (a) 1010101 (b) 1000001 3. Check each of the even parity codes for an error. (a) 100010101 (b) 1110111001 [ESRB rroustesHootine In this section, the problem of decoder glitches is introduced and examined from a troubleshooting standpoint. A glitch is any undesired voltage or current spike (pulse) of very short duration. A glitch can be interpreted as a valid signal by a logic circuit and may cause improper operation. After completing this section, you should be able to ‘= Explain what a glitch is * Determine the cause of glitches in a decoder application = Use the method of output strobing to eliminate glitches ‘The 74L.S138 was used as a DEMUX in the data transmission system in Figure 6-60, Now the 74HC138 is used as a 3-line-to-8-Hine decoder (binary-to-octal) in Figure 6-62 to illustrate how glitches occur and how to identify their cause. The AA\Ay inputs of the de ‘coder are sequenced through a binary count, and the resulting waveforms of the inputs and ‘outputs can be displayed on the screen of a logic analyzer, as shown in Figure 6-62. Ay tran- sitions are delayed trom A transitions and A transitions are delayed from Ay transitions, This commonly occurs when waveforms are generated by a binary counter, as you will lea in Chapter 8 ‘The output waveforms are correct except for the glitches that occur on some of the out- put signals, A logic analyzer or an oscilloscope can be used to display glitches, which are normally very difficult to see. Generally, the logic analyzers preferred, especially for low repetition rates (less than 10 kFiz) andor irregular occurrence because most logic ana- lyzers have a glitch capture capability. Oscilloscopes can be used to observe glitches with346 = FUNCTIONS OF COMBINATIONAL LOGIC > FicuRe Decoder waveform: with output glitches 2 Point Poin — i | & | a | = a | ap— oe | a = at | reasonable success, particularly if the glitches occur at a regular high repetition rate (ereater than 10 kHz). ‘The points of interest indicated by the highlighted areas on the input waveforms in Figure 6-62 are displayed as shown in Figure 6-63. At point I there is a transitional state Point 2: waveforms om expanded time hase Point 3: waveforms on expanded tie hase Ay HIGH Ay AsLOW"y Ady dg LOW 'fAeAs LOW: 4; HIGH An i a a, 3 a Point 1: waveforms on expanded tae base JX. Point waveforms on expanded ine base F Awd ds LOW 4 LOW: 4), As HIGH 4, 4) LOW: Ay HIGH a, oe 7 a FIGURE Decoder waveform dsplys showing how transitional input tates produce glitches inthe output waveforms 63TROUBLESHOOTING = 347 ‘0 000 due to delay dtferencs in the waveforms. This eauses the frst glitch on the 0 out- putof the decoder. At point 2 there ae two transitional sates, 010 and 000. These cause the sliteh on the 2 output ofthe decoder and the second glitch onthe output, respectively. At Point 3 the transitional state is 100, which causes the frst glitch onthe 4 output of the de- oder. At point 4 the two transitional states, 110 and 100, result in the liteh onthe 6 out- putand the second glitch on the 4 output, respectively. (One way to eliminate the glitch problem is method called strobing, in which the de- coder is enabled by a strobe pulse only during the times when the waveforms arc notin tan- sition, This method is illustrated in Figure 6-64, < Figure ‘Application ofa tobe waveform to climinate glitches on decoder outputs BINOCT EN TAC f= eee REVIEW 1. Define the term glitch, 2. Explain the basic eause of glitches in decoder logic. 3. Define the term strobe. ‘Troubleshooting problems that are keyed to the CD-ROM are available in the Multisim Troubleshooting Practice section of the end-of-chapter problems. 8 In addition to glitches that are the result of propagation delays, a you have seen in the cate of a decoder, other types of unwanted note spikes can ako be a problem, Current and voltage spikes on the Vec and ground lies are caused bythe fat sutching waveforms in digital circuits, This problem can be minimized by proper printed circuit board layout. Switching spikes can be absorbed by decoupling the cicult board with a1 pF capacitor from Vec to ground. Ako, smaller decoupling capacitor (0.022 pF to 0.1 if) should be dliteibuted at various points between Vec and ground over the circuit board. Decoupling should be done especially near devices that are switching at higher rates ord loads such as exciton, counters, buffers, and bus drivers348 = FUNCTIONS OF COMBINATIONAL LOGIC light fora minimum of25 seraslongas__interalof 25s and 4 that are required thee no vehicle on the side sueet.The inthe stem and to generate a clock side steot to have a green light unt signal for ying the tem (timing there ino vehicle on the side street orfor__ circuit). The time iatenak (lng and ‘maximum of255.There to bea4s short) andthe vehie sensor ar inputs ‘auton light (yellow) between changes __t the sequential logic because the {rom green to red on both the main treet sequencing of states is 2 function ofthese and on the side street. These requirements variables. Logic circuits are abo needed to ee areilustated inthe pictorial diagram in determine which ofthe four states the Figure <8. system isin at any given time, to generate the proper outputs to the lights (tate Developing » Block ‘decoder an light output logic), and to Diagram ofthe Sytem inate the long and short time intervals From the requirement, you can develop » Interface circuits are included in the eo) aerators ieee tet block diagram ofthe stem. Fist, you traffic light and interface unit to convert begin working witha traffic ight control know thatthe ystem must controlsie the output levels ofthe light output logic ‘system. ln this section, the system Afferent pats of lights. These ae the red, _to the voltages and current required to Tequitements are establihed a general yellow, and areen lights for bath directions turn on exch of the lights Figure 6-67 i block diagram is developed, and a state more detailed block diagram showing digram is created to define the sequence thete exential elements ‘ef opention Aportion ofthe stem side treet Ako, you Know that there involving combinational logic is designed __ one external input (other than power) __Ths Stats Disgram and methods of testing are considered, ‘fom aside treetvehicle senor Figure Astatedingram graphically shows the Testnkgsndiequcinipatirwaftie. | 6H6keminmelbedk dayem tevng_ | eqn of rts yen nd Be ‘ptomvabedeotethinGhapten the reutenents Secon ain eg eae enters | eaetee ee eter dingo you can bogs inthe | unl Fre 65 afm of ae neo rt Reqs Hei Hapa initioes se) laiopia beat fais Reece Aiken oie bcseol nb | Webasto | eee icce ieee ees aye ela eral eeeret eee tiesto cco si hs | gain ma esd8 A oro | on oie eee pean eT eel ee Main" Side Main Side Main Maa Se Fire state: 25 seconds Second tat: 4 seconds ‘Third stat: 28 seconds Fourth state: 4 seconds ‘minimum or as long #5 reaximu or ui there is no vehicle on there 0 sehile on side stret side FIGURE 6-65. Requirements fr the traffic light sequence.DIGITAL SYSTEM APPLICATION = 349 a tl LE ‘Traffic light and ‘A minimal sytem black diagram. inweace unit “Traffic light control logic ost Main Yellow nino el Green sensor ay Side Yellow Green ‘Traffic Hight control loge ‘Trafic Hight and inriace unt Combinational ope Sequential oie Ret Vehicle Main Yetlow ie oa . vl ‘input ae 8) Green Red I Sige} Yew een Shor Tong Clock Timing circuits po Shon gee [leompeteaintischpier [E] completed in Chaper7 [Z] comple in Chapter ‘A Figure 6-67 ‘System block diogram showing the evsential element, the variables that determine how the ss- | ® Vehicle present onside street = V, ‘The we of complemented variables tem sequences through its tates must be | indicates the opposite conditions. For defined, These variables and their symbol ‘empl, Vindicates that there is no are listed 2 follow 5 4 ctimer (short times) ton = Ty | vehicle on the side set, T; indicates the 5 25 stimer (long timer) on = T,350 = FUNCTIONS OF COMBINATI long tines fT, nda the short tine sof Description ofthe State Diagram A state diagram is show in Figure 6-68. Each ofthe four state it labeled acconding to the 2-bit Gray code sequence as indicated by the circles. The looping arow at each state indicates thatthe stem remainsin that tate under the condition defined by the sociated variable or expreson. Each ofthe arrows going fom one tate tothe ret indicates a tate tranition under the condition defined bythe awociated vari able orexpresion, First state The Gray code for this state 1400. The main street light green and the side sret light i red, The sstem remaine in this state for at least 25s when the long timers on ort long as there isno vehicle con the side street (7, + ¥,). The system goes to the next state when the 25 timer fs off and there ia vehicle onthe side street (TM). Second state The Gray code for this state 01, The main sret light ityellow (coution) and the side sveet light ised. The FIGURE 6-68 | State diagram forthe trafic ight contol stem showing the Gray |code sequence. JONAL LOGIC ptm cain this ate for 4s when the | shortimer ton (T.) and goes to the next ate when the short Une goes off). “Third state. The Geay code for this state fs 11.The main street light ised and the side sect light is green, The syste re= ‘mains inthis state when the ong timer is ‘on and there isa vehicle on the side street (7). The stem goes tothe next state when the 25 shave elapsed or when there {sno vehicle onthe sie steet, whichever comes fist (T+ V) Fourth state The Gray code for this state is 10, The main treet light ed and the side street ight is yellow The system remains in this state for 4 when the short timer ison (T,) and goes back to the fist state when the short timer g0es off (7) ‘The Combinational Logic The focus in this chapters stem application i the combinational logic portion of te block diagram of Figure 6-67. The timing and the sequential logic rcs will be the subjects ofthe system | application sections in Chapter 7 and 8. nist Fourth sto Main: rd Side: “ZA Main: rt Sieigeen i A block diagram forthe combinational {logic portion ofthe system is developed as ‘the fist step in designing the logic. The thre functions tht this logic must perform are defined a follows, and the resulting clagrom with a block or exch ofthe tee fonctions it shown in Figure 6-69 1 State Decoder Decodes the 2-bit {Gray code from the sequential logic to determine which ofthe four states the system iin 1 Light Output Logic Uses the decoded tate to acthate the appropriate trafic light forthe main and side treet light units 1 Trigger Logic Uses the decoded states to produce signals for propetly Initiating (triggering) the long timer ‘and the short timer. Implementation of the Combinational Logic Implementing the Decoder Logic The state decoder portion has two inputs | (2+bit Gray code) and an output for exch \ atin setiow SieteDIGITAL SYSTEM APPLICATION = 357 c Inputs Gays) Sat decoder Tian opt one ea} we 30;J 4 Min Yow Pa $% sme) 50: Green f+ MG Lig onus é toimerace St ee | Reb 98 —circuitin ight ont 504 side} Yalow + sy ‘reea | > 5c | Figul FIGURE 6-70 ‘The state decoder logic ofthe four states, at shown in Figure 6-70, ‘The two Gray code inputs are designated ‘Sand 5, and the four state outputs are labeled 50,, 0, 50,, and 50, The Boolean exprenions forthe state outputs are 2 follows Long “Trigzer logic short f= Block diagram ofthe combinational logic oe Implementing the Light Output Logie ‘Te light output logic takes the four state outputs and produces six outputs for activating the taffic lights. Theve outputs are designated MR, MY, MG (for ‘main red, main yellow, and main geen) ‘and SR, SY, SG (Forside red, side yellow, and side green). Referring to the truth table in Table 6-11, you can see that the tuaffic light outputs can be expresed a5 “The truth table fr thi state decoder logic ‘sshown io Table 6-11 MR = $05 + 50, ™ $0 80, 90, SR = $0, + 50, 51 = 50, 5G = 50, “The output logic it implemented a shown fn Figure 6-71 Implementing the Trigger Logic The tigger logic produces two outputs. The dong outputs» LOW-to-HIGH vanstion thot triggers the 25 timing cic when the stem goes inte the ist (0) or tied states(11). The short output is LOW-to- MG = 50, HIGH transition that bigger the 4s timing352 = FUNCTIONS OF COMBINATION TABLE 6-11 Tuth table for the combinational logic. STATE INPUTS, Fe FIGURE 6-71 The ight output loge CURE ‘The uigge logic. 2 circuit when the stem goes nto the sec- ‘nd (01) or fourth (10) states. The trigger ‘outputs ae shown in Table 6-11 and in «equation form 2 follows: Long tigger = 50, + $0, Short ger = SO, + 504 “The trigger lope shown in Figure 672{9). Table 6-11 abo shows thatthe Long output and the short output are complements, s0 the loge can alo be RY NAL LOGIC. re Cranes ead Ce) ‘Ste pss ative HIGH ad igh ups a sve HIGH MA stan oma soso 5G foro oe reno 50, y a wy se sv sc » implemented with one OR gate and one Jverter as shown in part). Figure 6-73 shows the complete combinational logic that combines the state decoder light ovtput logic, and trigger loge System Asignment 5 Activity 1 Apply waveforms forthe 2-bit Gaay code on the Sand 5, inputs ofthe => = DDo— sien ess ica co combinational logic and develop all of the output waveforms ® Activity 2 Show how you would implement the combinational logic with 74XX functions Optional Activity Waite a VHDL program describing the combinational logic> Figure 6-74 SUMMARY = 353 Long rigger Shon tigaer "= Half-adder and full-adder operations are summarized in Figure 6-74. "Logie symbols wth pin numbers forthe ICs used in this chapter are shown in Figure 6-75. Pin designations may differ from some manufacturers’ data sheets. ‘= Standard logic functions from the 74XX series are available for use ina programmable logic design. Hater Fulhadser = is la te] [eA354. = FUNCTIONS OF COMBINATIONAL LOGIC pe pe aaa as iE spas tea " spas q a) Se A FloURE 6-75 DERE cers nother bot ers in the chapter ar defined inthe end-of-book sos. Caseading Connecting the ourpu of one device to the input ofa similar device, allowing one device to drive another in order to expand the operational capability Decoder A digital circuit that converts coded information into a familiar or noncoded form. Demultiplexer (DEMUX) A circuit tha switches digital data from one input line to several output lines ina specified time sequence. Encoder 4 digital ciruit that converts information wo coded form. Full-adder A digital circuit that ad two bits and an input carry to produce a sum and an output carry Giliteh 4 voltage or current spike of short duration, usually unintentionally proxluced and unwanted. Half-adder A digital cireuit that adds two bits and produces a sui and an output cary Tteannot han= dle input carries LLook-ahead carry A method of binary addition whereby carries From preceding adder stages are an- ticipated, ths eliminating carry propagation delays. Multiplexer (MUX) A circuit that switches digital data from several input ines onto a single output line in a specified time sequence. Parity bit bit attached to each group of information bits to make the total numberof Is odd or even for every group of bits.SELF-TEST = 355 Priority encoder An coder in which only the highest value input digit is encoded and any other ac- tive input is ignored, jpple carry A method of binary addition in which the ourput cary from each adder becomes the in- pt carry of the next higher-order adder. FEE ec oe atthe end ofthe chapter. 1. Aalders characterized by (9) so inputs and two ouputs_(B) three inputs and wo outputs (6) two inputs and three outputs (@) two inputs and one output 2. A full-adder is characterized by (2) two inputs and two outputs (b) three inputs and wo outputs () evo inputs and tree outputs (@) to inputs and one output 3. The inputs toa full-adder areA = 1, B= 1, Cy = 0. The outputs are IANA MELO (©) E=0, Cu (@) E=0,6u=0 4. A 4-bit parallel adder can add (a) two 4bic binary numbers (b) two 2-bit binary numbers (6) four bits ata time (2) four bits in sequence 8, To expand a 4-bit parallel adder to an 8-bit parallel add (4) use four dit adders with no interconnections You must () use two 4 elders and connect the sum outputs of one to the bit inputs ofthe other (6) use cight 4-bit adders with no interconnections (2) use wo 4-it adders with the cary output of one connected tothe camy input ofthe other 6, Ifa THHC8S mag tude comparator has A = 1011 and B = 1001 on its inputs, the otpets are (@) A>B=0,AB=1,AcB=0.A=B=0 (©) A>B=1AB=0,AcB=0,4 7. Ifa 1-of-16 decoder with actve-LOW outputs exhibits a LOW on the decimal 12 output, what ae the inputs? (8) AAyAyAy = 1010 (b) AYAA\Ay= 1110 (©) AAD 1100 (@) AAsAyAo™ 0100 8, A BCD-to-7 segment decoder has 0100 on its ints. The active outputs are ache OWheke Oboes Mhdas Ian octl-t-binary priority encoder has is 0,2, 5, and 6 inputs atthe ative level, he aetive- HIGH binary output is (@) 110) 010) 101 @) 000 16, In general, a muliplexer has (4) one data input, several data outputs, and seetion inputs () one data input, one daa output, and one seletion input (6) several data inputs, several data outputs and seletion inputs (4) several data inputs, one data output, and selection inputs U1, Data selectors ae basically the same a5 {a) decoders (b) demultiplexers (@) multiplexers (@) encoders 12, Which ofthe following codes exhibit even party? (@) 10011000) 01114000.) HINT (a) 11010101 @) all (0) both answers (band (e) 9.356 = FUNCTIONS OF COMBINATIONAL LOGIC DET eto ts rumored prensa atthe end ofthe book SECTION 6-1 Basie Adders 1, For the full adder of Figure 6-4, determine the logic state (I or 0) at each gate outpt forthe following inputs: (@)A=1B=1.G.= 1 (D)A=O.B=1,6g=1 (©) A=0.8=1,6q= 2, What are the fuller inputs that will produce each of the Following outputs: (a) F=0,Cy=0 — (b) B= 1, Coy CE=LCu=1 GB E=0,Cq=1 43. Determine the outputs of a fll-adder for each of the following inputs (@) A=1,B=0,6,=0 (b) A=0,8=0,6,=1 (A=0.B=16,=1 @)A=1B8 Binary Adders 4. For the parallel adder in Figure 6-16, determine the complete sum by analysis ofthe logical ‘operation of the ciruit Verify your result by longhand addition ofthe (wo input numbers, > FIGURE 6-76 > FIGURE 6-77 66. The input waveforms in Figure 6-78 are applied to a -bit adder; Determine the waveforms for the sum and the output cary in relation to the inputs by constructing a timing diagram, URE 6.> FIGURE 6-79 > FIGURE PROBLEMS = 357 1. The following sequences of bits (right-most bit ist) appear on the inputs to 4-bit parallel adder, Determine the resulting sequence of bits on each sum output A 1001 A L110 Ay 0000 A 1011 a nu B 100 % 1010 a oo10 8. Inthe process of checking a 741.8283 4-bt parallel adder, the following voltage levels are ‘observed on its pins: |-HIGH, 2-HIGH, 3-HIGH, 4-HIGH, 5-LOW, 6-LOW, 7-LOW, 9-HIGH, 10-LOW, 11-HIGH, 12-LOW, 13-HIGH, 14-HIGH, and [5-HIGH. Determine if the IC is functioning properly SECTION 6-3 Ripple Carry Versus Look-Ahead Carry Adders 9. ach ofthe eight fulladders in an 8-bt parallel ripple carry adder exhibits the Following propagation delays AtoEand Cu 40-ns BioLand Cy: 40 ns CptoE 35s C10 Cu? 25.8 Determine the maximum total time for the alton of two 8-bit numbers, 10, Show the additonal logic ctcutry necessary to make the +-bit look-ahead carry adder in igure 6-18 into a S-bit adder. SECTION 6-4 Comparators 11, The waveforms in Figure 6-79 are applied tothe comparator as shown. Determine the ouput ) waveform, Poo 12, For the 4-it comparator in Figure 6-80, plot each eutput waveform forthe inputs shown, The ‘outputs are active-HIGH, [7 L COMP a>a}— Ase acel— ap, THHCRS358 = FUNCTIONS OF COMBINATIONAL LOGIC 13, For each set of binary numbers determine the output states forthe comparator of Figure 6-22. (a) AvsA\Ay= 1100 (b) AvtaAyAy = 1000 (6) AvAyA,Ay = 0100 BBB By = 1001 BBB By By = 0100 SECTION 6-5 Decoders 14. When « HIGH is on the output of each of the decoding gates in Figure 6-81, what isthe binary ‘code appearing onthe inputs? The MSB is A, > FIGURE 6-81 © @ 18. Show the decoding logic foreach ofthe following codes if an actve-HIGH (1) output is require: (a) 1101) 1000 (@) LION @) 1100 fe) 101010 (6) 111110 ¢g) 00101 (A) 1110110 16. Solve Problem 15, given that an sctive-LOW (0) ourpat is required. 17. You wish to detect ony the presence ofthe codes 1010, 1100, 0001, and 1011. An ative HIGH output is reqited to indicate ther presence. Develop the minimum decoding logic with single output that wll indicate when any one ofthese codes son the inputs. For anyother eae, the output must he LOW. 18, Ifthe input waveforms are applied tothe decoding logic as indicated in Figure 6-82, sketch {he outpt waveform in proper relation tothe inputs. 19, BCD numbers are applied sequentially to the BCD-to-dee I decoder in Figure 6-83. Draw a timing diagram, showing each output in the proper relationship with te others and withthe inputs.> Figure 6-83 > FIGURE SECTION 6-6 SECTION 6-7 PROBLEMS = 359 rong Aone oe ener ee ee cree eae a : Tosa coe Ta ze ASS An ee T I i | i Ai 3 At 1 ees ese ee ‘ Se ene ee 24 eel sb>— ss a am Tice 20. A 7-segment decoderidrver dives the display in Figure 6-84. I'he waveforms are applied as indicated, determine the sequence of digits that appears on the display. aaa lea TCD genoa ZS reins | ie SL 21. For the decimal-o-BCD encoder logic of Figure 6-38, assume thatthe 9 input and the 3 input are both HIGH, What isthe utpot code? Is ita valid BCD (8421) code? 22, A TAHC147 encoder has LOW levels on pins 2,5, and 12. What BCD code appears onthe ‘outputs if all he other inputs are HIGH? Code Converters 23, Convert the following decimal numbers to BCD and then to binary. @2 8 OB @%» OR 24, Show the logic required to convert a 10-bit binary number to Gray code, and use that logic to convert the following binary numbers to Gray code: (@) 1010101010 (by 1111100000 (€) OoOAODLTIO — (@) LHLITLNIT 25. Show the logic required to convert 10-bit Gray code to binary, and use that loge to convert the following Gray code words to binary (a) 1010000000 (b) 0011001100 (@) 1111000111 (@) 0900000001360 = FUNCTIONS OF COMBINATIONAL LOGIC SECTION 6-8 Multiplexers (Data Selectors) 26, For the mukiplexer in Figure 6-85, termine the outpat for he following input ae: Dy=0,D,=1,Dy=1,Dy=0.5= 1,5; =0. iGuRE 6-85. 27, Ifthe datasolect inputs to the multiplexer in Figure 6-85 are sequenced as shown by the ‘waveforms in Figure 6-86, determine the output waveform with the data inputs specified in Problem 26. > Ficune 6-86 4 ica ; ~y 5 ' 28, The wavefoms in Figure 6-87 are observed on the inputs ofa 7ALS1S1 input miler Sketch the Y output waveform, see SE ei iar rs Pes Bet ea as etter Brae t Teale ea ale see agape [nist teet pa PSS Re ete cE St wa] aie eG leteiiegiatice lnm tir da Sic af ce at at tt ! SECTION 6-9 Demuttiplexers 29, Develop the total timing diagram (inputs and outputs) fora 74HC154 used ina demukiplexing pplication in which the inputs are as follows: The data-select inputs are repetitively sequenced through a straight binary count beginning with 0000, and the data inpt isa serial data stream carrying BCD data representing the decimal number 2468. The least significant ligt (8) is first in the sequence, with is LSB fis, and it should appear in the first 4-bit Positions of the output.PROBLEMS = 361 SECTION 6-10 Parity Generators/Checkers 30. The waveforms in Figure 6-88 are applied tothe 4bit parity loge. Determine the output waveform in proper relation tothe inputs. For how many bt times does even parity our, and how i it indicated? The timing diagram includes eight bit times. bp rcune 6-18 “TT |, a ee ee =>! en 1 meet 3M, Determine the © Even andthe E Oud outputs of a 74.S280 9-bit parity generatorichecker for ‘the inputs in Figure 6-89. Refer tothe funetion table in Figure 6-89. pete ee Sse ey ncaa eo a | ec SECTION 6-11 Troubleshooting 32 The fll-adderin Figure 6-90 is tested under all input conditions with the input waveforms shown. From your observation of the Zand Cy. waveforms, i it operating propery, and if no, ‘what isthe most Fkely fault? A FIGURE 6-90362 = FUNCTIONS OF COMBINATIONAL LOGIC @ [33 List the possible faults for each decoder/dsplay in Figure 6-91, ana aa roa ear) soe Ba : ee eS (leee FIGURE 6-92 BCD ten dist BCD units ii i Bh Sasa ral — EEE eens % x 5 Gon 432 T T fart 6 ARIS Le | "it binary opt 36. Forte display multiplexing system in Figure 6-S2, determine the most ikely cause or causes fox each of the following symptoms a) The B-digit (MSD) display does noc turn on a al. (b) Neither 7segment display turns on> TABLE 6-12 PROBLEMS = 363 (©) The fsegment ofboth displays appears tobe on all the time: (@) There isa visible licker on the displays Develop a systematic procedure fully test the 74LS151 data selector IC. During the testing ofthe data wansmission system in Figure 6-60, a code is upplied to the Dy ‘through D, inputs that contains an odd numberof Is A single bit error is deliberately introduced on the serial data transmission line between the MUX and the DEMUX, but the system does not indicate un eror (err output = 0) Aller some investigation, you eeck the Inputs tothe even parity checker and find that De through D, contain an even number of Is, as you would expect. Also, you find thatthe D; party bit sa. What are the posible reasons for the system not indicating the error? eS 39. In general describe how you would fully test the data transmission system in Figure 6-60, and specify 8 method fr the introduction of party errors Digital System Application 40. The light output logic can be implemented in the system application with Fixed-function logic using a 74LS08 with the AND gates operating as negative-NOR gates. Use a 741.S00 (quad AND gates) and any other devices that may be required to produce ative-LOW outputs for the given inputs 41. tmplement the Tight output logic with the 74LS00 if active-LOW outputs are required Special Design Problems 42. Modify the design of the 7-segment display multiplexing system in Figure 6-52 to ‘accommodate wo additional digits. 43. Using Table 6-2, write the SOP expressions forthe Eand Cy ofa fulladder. Use a Karnaugh ‘map to minimize the expressions and then implement them with inverters and AND-OR logic, ‘Show how you can replace the AND-OR logic with 74LS1S1 data selectors 444, Implement the Iogie function specified in Table 6-12 by using a 74LSIST data selector.364 = FUNCTIONS OF COMBINATIONAL LOGIC 45, Using two ofthe 6 position adder modules from Figure 6-14, design a 12-position voting system. 46, The adder block inthe tablet-counting and control system in Figure 6-93 petforms the addition ofthe 8-bit binary number from the counter and the 16-bit binary number from Register B. The result from the adder goes back into Register B. Use 74L8283s to implement this function and draw a complete logic diagram including pin numbers. Refer to Chapter | system application to review the operation, 447, Use 74HC85s to implement the comparator block in the tablet counting and control system in Figure 6-93 and draw a complete logic diagram including pin numbers. The comparator ‘compares the §-bit binary number (actually only seven bits are required) from the BCD-0- binary converter with the 8-bt inary number from the counter, 48. Two BCD-to-7-segment decoders are used inthe tablet-counting andl control system in Figure 6-93. One is required to drive the 2-digitrablts/botle display and the other to drive the 5-digit ora tablets bottled display. Use 741S47s to implement each decoder and draw a ‘complete logic diagram including pin numbers. mf — =e i ed a rh a sum” rege ina ; _ code Decoser sneer B Biawy —P acdw toBCD 7% csi ‘Mux Testis Switching sequence ‘contain A FIGURE 6-93 49. ‘The encoder shown in the system block diagram of Figure 6-93 encodes each decimal key B=1,AcB=0,A=B=Owhend = 1011 and B= 1010 2. Right comparator pin 7: A-B Left comparator: pin 7: A < B = 0; pin 6: pin S:A > 2 SECTION 6-5 Decoders 1, Output Sis active when 101 ison the inputs. 2. Four T4HC1S#s are used to decode a 6-bit binary number. 3._ Active-LOW output drives a common-cathode LED display SECTION 6-6 1LAy= 1A, =0,4 (0) No, this is nota valid BCD code, (©) Only one input cam be active fora valid ouput. 2 (@) Ay=0,Ay=1,A,= 1,Ay=1 (b) The output is 0111, whichis the complement of 1000 (8)366 = FUNCTIONS OF COMBINATIONAL LOGIC SECTION 6-7 Code Converters 1. 10000101 (BCD) = 1010101; 2. An 8-bit hinary-1-Gray converter consists of seven exclusive-OR gates in an arrangement like ‘that in Figure 6-43. SECTION 6-8 Multiplexers (Data Selectors) 1, The outputs 0 2, (a) 7ALSIS7: Quad 2-input data selector (b) 7ALS151: 8-input data selector ‘3. The data output alternates between LOW and HIGH as the data-select inputs sequence through the binary tates. 4. (a) The 74HC157 multiplexes the wo BCD codes to the 7-segment decoder. (b) The 7ALSA7 decodes the RCD to energize the display (©) The 74LS139 enables the 7-segment displays alternately SECTION 6-9 Demuttiplexers 1, A decoder canbe used as & multiplexer by using the input ines for data selection and an Enable line for data input. 2, The outputs are all HIGH except Dp, which is LOW, SECTION 6-10 Parity Generators/Checkers 41. (@) Even parity: 1110100) Even parity: 901100011 2 (a) Oda parity: 11010101 ¢b) Oa parity: 11000001 3. (a) Code is correct, our Is. (b) Code isin error, seven Is SECTION 6-11 Troubleshooting 1. glitch is a very shor-duration voltage spike (usually unwanted) 2, Glitches are caused by transition states, ‘3. Surobe isthe enabling ofa device fora specified period of time when the device is not in "RELATED PROBLEMS FOR EXAMPLES — 61 E=1,64=1 622,=0,%- 02-1001 6-3 1011 + 1010= 10101 6-4 See Figure 6-94, > FIGURE 6-94 TIT am TTTT LittiiiyANSWERS = 367 6-5 See Figure 6-95. > FIGURE 6-95 [Do osc 66 A>B=0,A=B=0,A FIGURE 6-96 Lit i Litt iit L i 6-8 See Figure 6-97. 6-9 Output 22 > FIGURE 6-10 See Figure 6-98, > Ficure 6-98368 = FUNCTIONS OF COMBINATIONAL LOGIC G11 Allinputs LOW: Ay = 0,4, = 1, Ay Al inputs HIGH: All ourputs HIGH, 6-12. BCD 01000001 cv000001 1 coro1on0 40 Biny oi0i001 a1 6-13 Seven excuse OR gates 614 See igure 6-9. raed eas gees hg el ea elena? oaera | G15 Dy S,= 0.5," 0,5; = 05 DeS,=0,5:= 1,5," 0,5) 1S) = 0,5) DeS= 1S) Dui y= 1,8," 1,5, =0.5= 1 6-16 See Figure 6-100, we ee, 6-17 See Figure 6-101 Figure J P= fists> FIGURE 6-18 See Figure 6-102. esto a an ' Fi gra ate a A el “SELF-TEST L@ 26) 30 4@ 9 @) WG) 1) 124 5@) 6.0) 20) ANSWERS = 369 8.)

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