0% found this document useful (0 votes)
52 views6 pages

MAC12D, MAC12M, MAC12N Triacs: Silicon Bidirectional Thyristors

datasheet
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
52 views6 pages

MAC12D, MAC12M, MAC12N Triacs: Silicon Bidirectional Thyristors

datasheet
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 6

MAC12D, MAC12M, MAC12N

Preferred Device

Triacs
Silicon Bidirectional Thyristors
Designed for high performance fullwave ac control applications
where high noise immunity and commutating di/dt are required.
http://onsemi.com
Features

TRIACS
12 AMPERES RMS
400 thru 800 VOLTS

Blocking Voltage to 800 Volts


OnState Current Rating of 12 Amperes RMS at 70C
Uniform Gate Trigger Currents in Three Quadrants, Q1, Q2, and Q3
High Immunity to dv/dt 250 V/ms Minimum at 125C
High Commutating di/dt 6.5 A/ms Minimum at 125C
Industry Standard TO220 AB Package
High Surge Current Capability 100 Amperes
PbFree Packages are Available*

MT2

MT1
G

MARKING
DIAGRAM

MAXIMUM RATINGS (TJ = 25C unless otherwise noted)


Rating

Symbol

Peak Repetitive OffState Voltage (Note 1)


(TJ = 40 to 125C, Sine Wave,
50 to 60 Hz, Gate Open)
MAC12D
MAC12M
MAC12N

VDRM,
VRRM

On-State RMS Current


(All Conduction Angles; TC = 70C)

IT(RMS)

12

Peak Non-Repetitive Surge Current


(One Full Cycle, 60 Hz, TJ = 125C)

ITSM

100

I2t

41

A2sec

PGM

16

PG(AV)

0.35

Circuit Fusing Consideration (t = 8.33 ms)


Peak Gate Power
(Pulse Width 1.0 ms, TC = 80C)
Average Gate Power
(t = 8.3 ms, TC = 80C)

Value

Unit
V
MAC12xG
AYWW

400
600
800

TJ

40 to +125

Storage Temperature Range

Tstg

40 to +150

Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. VDRM and VRRM for all types can be applied on a continuous basis. Blocking
voltages shall not be tested with a constant current source such that the
voltage ratings of the devices are exceeded.

*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

December, 2005 Rev. 4

3
x
A
Y
WW
G

= D, M, or N
= Assembly Location
= Year
= Work Week
= PbFree Package

PIN ASSIGNMENT

Operating Junction Temperature Range

Semiconductor Components Industries, LLC, 2005

TO220AB
CASE 221A09
STYLE 4

Main Terminal 1

Main Terminal 2

Gate

Main Terminal 2

ORDERING INFORMATION
Package

Shipping

MAC12D

Device

TO220AB

50 Units / Rail

MAC12DG

TO220AB
(PbFree)

50 Units / Rail

MAC12M

TO220AB

50 Units / Rail

MAC12MG

TO220AB
(PbFree)

50 Units / Rail

MAC12N

TO220AB

50 Units / Rail

MAC12NG

TO220AB
(PbFree)

50 Units / Rail

Preferred devices are recommended choices for future use


and best overall value.

Publication Order Number:


MAC12/D

MAC12D, MAC12M, MAC12N


THERMAL CHARACTERISTICS

Thermal Resistance,

Characteristic

Symbol

Value

Unit

JunctiontoCase
JunctiontoAmbient

RqJC
RqJA

2.2
62.5

C/W

TL

260

Maximum Lead Temperature for Soldering Purposes 1/8 from Case for 10 Seconds

ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted; Electricals apply in both directions)
Characteristic

Symbol

Min

Typ

Max

Unit

IDRM,
IRRM

0.01
2.0

mA

Peak OnState Voltage (Note 2) (ITM = "17 A)

VTM

1.85

Gate Trigger Current (Continuous dc) (VD = 12 V, RL = 100 W)


MT2(+), G(+)
MT2(+), G()
MT2(), G()

IGT
5.0
5.0
5.0

13
13
13

35
35
35

Hold Current (VD = 12 V, Gate Open, Initiating Current = "150 mA)

IH

20

40

Latch Current (VD = 24 V, IG = 35 mA)


MT2(+), G(+)
MT2(+), G()
MT2(), G()

IL

20
30
20

50
80
50

0.5
0.5
0.5

0.78
0.70
0.71

1.5
1.5
1.5

OFF CHARACTERISTICS
TJ = 25C
TJ = 125C

Peak Repetitive Blocking Current


(VD = Rated VDRM, VRRM, Gate Open)
ON CHARACTERISTICS

Gate Trigger Voltage (Continuous dc) (VD = 12 V, RL = 100 W)


MT2(+), G(+)
MT2(+), G()
MT2(), G()

mA

mA
mA

VGT

DYNAMIC CHARACTERISTICS
Rate of Change of Commutating Current
(VD = 400 V, ITM = 4.4A, Commutating dv/dt = 18 V/ms, Gate Open,
TJ = 125C, f = 250 Hz, No Snubber)

(di/dt)c

6.5

A/ms

Critical Rate of Rise of OffState Voltage


(VD = Rated VDRM, Exponential Waveform, Gate Open, TJ = 125C)

dv/dt

250

500

V/ms

Repetitive Critical Rate of Rise of On-State Current


IPK = 50 A; PW = 40 msec; diG/dt = 200 mA/msec; f = 60 Hz

di/dt

10

A/ms

2. Pulse Test: Pulse Width 2.0 ms, Duty Cycle 2%.

http://onsemi.com
2

MAC12D, MAC12M, MAC12N


Voltage Current Characteristic of Triacs
(Bidirectional Device)
+ Current

Symbol

Parameter

VTM

VDRM

Peak Repetitive Forward Off State Voltage

IDRM

Peak Forward Blocking Current

VRRM

Peak Repetitive Reverse Off State Voltage

IRRM

Peak Reverse Blocking Current

VTM

Maximum On State Voltage

IH

Holding Current

on state
IH

IRRM at VRRM

off state
IH
Quadrant 3
MainTerminal 2

VTM

Quadrant Definitions for a Triac


MT2 POSITIVE
(Positive Half Cycle)
+

(+) MT2

Quadrant II

(+) MT2

() IGT
GATE

Quadrant I

(+) IGT
GATE
MT1

MT1

REF

REF
IGT

+ IGT
() MT2

Quadrant III

Quadrant 1
MainTerminal 2 +

() MT2

Quadrant IV

(+) IGT
GATE

() IGT
GATE

MT1

MT1

REF

REF

MT2 NEGATIVE
(Negative Half Cycle)

All polarities are referenced to MT1.


With inphase signals (using standard AC lines) quadrants I and III are used.

http://onsemi.com
3

+ Voltage
IDRM at VDRM

MAC12D, MAC12M, MAC12N


1.10
VGT, GATE TRIGGER VOLTAGE (VOLT)

IGT, GATE TRIGGER CURRENT (mA)

100

Q3
Q2
Q1
10

1
40 25 10

5 20 35 50 65 80 95
TJ, JUNCTION TEMPERATURE (C)

110

1.00 Q3
0.90 Q1
0.80 Q2
0.70
0.60
0.50
0.40
40 25 10

125

125

100

MT2 POSITIVE

10

LATCHING CURRENT (mA)

HOLDING CURRENT (mA)

100

MT2 NEGATIVE

1
40 25 10

5
20 35 50 65 80 95
TJ, JUNCTION TEMPERATURE (C)

110

Q2
Q1
Q3

10

1
40 25 10

125

P(AV), AVERAGE POWER DISSIPATION (WATTS)

125
120, 90, 60, 30

110

95
180
80
DC
0

5
20 35 50
65 80 95
TJ, JUNCTION TEMPERATURE (C)

110 125

Figure 4. Typical Latching Current


versus Junction Temperature

Figure 3. Typical Holding Current


versus Junction Temperature

TC, CASE TEMPERATURE (C)

110

Figure 2. Typical Gate Trigger Voltage


versus Junction Temperature

Figure 1. Typical Gate Trigger Current


versus Junction Temperature

65

5
20 35 50 65 80 95
TJ, JUNCTION TEMPERATURE (C)

4
6
8
10
IT(RMS), RMS ON-STATE CURRENT (AMP)

12

20

DC

18

180

16

120

14
12
10
8

60

30

4
2
0

Figure 5. Typical RMS Current Derating

2
4
6
8
10
IT(AV), AVERAGE ON-STATE CURRENT (AMP)

Figure 6. On-State Power Dissipation

http://onsemi.com
4

90

12

MAC12D, MAC12M, MAC12N

TYPICAL @
TJ = 25C

r(t), TRANSIENT THERMAL RESISTANCE


(NORMALIZED)

I T, INSTANTANEOUS ON-STATE CURRENT (AMP)

100

MAXIMUM @ TJ = 125C

10

MAXIMUM @ TJ = 25C

0.1

0.01

0.1

10
100
t, TIME (ms)

1000

Figure 8. Typical Thermal Response


0.1

0.5
1
1.5
2
2.5
3
3.5
4
4.5
VT, INSTANTANEOUS ON-STATE VOLTAGE (VOLTS)

Figure 7. Typical On-State Characteristics

http://onsemi.com
5

10000

MAC12D, MAC12M, MAC12N


PACKAGE DIMENSIONS
TO220AB
CASE 221A09
ISSUE AA

T
B

SEATING
PLANE

F
T

DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z

Q
1 2 3

H
K
Z
L

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.

G
D
N

INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045

0.080

STYLE 4:
PIN 1.
2.
3.
4.

MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15

2.04

MAIN TERMINAL 1
MAIN TERMINAL 2
GATE
MAIN TERMINAL 2

ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION


LITERATURE FULFILLMENT:
N. American Technical Support: 8002829855 Toll Free
Literature Distribution Center for ON Semiconductor
USA/Canada
P.O. Box 61312, Phoenix, Arizona 850821312 USA
Phone: 4808297710 or 8003443860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center
291 Kamimeguro, Meguroku, Tokyo, Japan 1530051
Fax: 4808297709 or 8003443867 Toll Free USA/Canada
Phone: 81357733850
Email: [email protected]

http://onsemi.com
6

ON Semiconductor Website: http://onsemi.com


Order Literature: http://www.onsemi.com/litorder
For additional information, please contact your
local Sales Representative.

MAC12/D

You might also like