Modelsim Tutorial
Modelsim Tutorial
Embedded Systems
Laboratory
EE 270
(Room#389)
CODE OF ETHICS
No eating or drinking is allowed inside lab
Switch off the lights and computers if not in
use
Use lab only for project and assignments
ModelSim
User-friendly software accepting VHDL and
Verilog.
Compatible with any Windows versions
Download free student version from the
below link:
http://www.mentor.com/company/higher_ed/m
odelsim-student-edition
Continued(Behavioral)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FULLADDER is
port (a, b, c: in std_logic;
sum, carry: out std_logic);
end FULLADDER;
architecture fulladder_behav of FULLADDER is
begin
sum <= (a xor b) xor c ;
carry <= (a and b) or (c and (a xor b));
end fulladder_behav;