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Advanced Digital Ic Design Design (Session 5) (SSSON5) : Verilog HDL (III) (Sequential Logic)

This document discusses sequential logic and finite state machines in Verilog HDL. It covers sequential blocks, timing parameters for sequential systems like minimum period and delay, the always block for sequential logic, importance of sensitivity lists, examples of coding a 74163 chip and a Moore vending machine as finite state machines in Verilog, techniques for state reduction and registering outputs to prevent glitches.

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Mohammad Seemab Aslam
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34 views18 pages

Advanced Digital Ic Design Design (Session 5) (SSSON5) : Verilog HDL (III) (Sequential Logic)

This document discusses sequential logic and finite state machines in Verilog HDL. It covers sequential blocks, timing parameters for sequential systems like minimum period and delay, the always block for sequential logic, importance of sensitivity lists, examples of coding a 74163 chip and a Moore vending machine as finite state machines in Verilog, techniques for state reduction and registering outputs to prevent glitches.

Uploaded by

Mohammad Seemab Aslam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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ADVANCED DIGITAL IC

DESIGN
(SESSION
(S
SS ON 5)

Verilog HDL (III)


(Sequential Logic)

Sequential Blocks
2

A Sequential System
3

Important Timing Parameters


4

System Timing Parameters


5

Minimum Period
6

Minimum Delay
7

The Sequential always Block


8

Importance of the
Sensitivity List
9

Example:
Verilog Code for 74163
10

Finite State Machines


11

Example:
A Moore Vender Machine
12

State Reduction
13

14

Verilog Code for the Moore


Vender Machine

15

Verilog Code for the Moore


Vender Machine (Continued)

16

Coding Alternative:
Two Blocks

FSM Output Glitching


17

18

Registered FSM Outputs


are Glitch-free

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