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INTRODUCTION TO
CMOS VLSI
DESIGN
LECTURE 15:
NONIDEAL TRANSISTORS
David Harris
Harvey Mudd College

Spring 2004
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OUTLINE
Transistor I-V Review
Nonideal Transistor Behavior
Velocity Saturation
Channel Length Modulation
Body Effect
Leakage
Temperature Sensitivity
15: Nonideal Transistors
Process and Environmental Variations
Process Corners
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Slide
3
CMOS VLSI Design
IDEAL TRANSISTOR I-V
Shockley 1st order transistor models
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Vgs Vt
V V V
ds
ds
dsat
Vds Vdsat
CMOS VLSI Design

V
I ds Vgs Vt ds
2
Vgs Vt
cutoff
linear
saturation
Slide
4
IDEAL NMOS I-V PLOT

180 nm TSMC process
Ideal Models
= 155(W/L)
Vt = 0.4 V
VDD = 1.8 V
Ids (mA)
mA/V2
400
Vgs = 1.8
300
Vgs = 1.5
200
Vgs = 1.2
100
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Vgs = 0.9
Vgs = 0.6
0
0.3
0.6
0.9
1.2
1.5
1.8
Vds
Slide
5
CMOS VLSI Design
SIMULATED NMOS I-V PLOT

180 nm TSMC process
BSIM 3v3 SPICE models
What differs?
250
Vgs = 1.8
200
Vgs = 1.5
150
Vgs = 1.2
Ids (mA)
100
Vgs = 0.9
50
Vgs = 0.6
0
0
0.3
0.6
0.9
1.2
1.5
Vds
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Slide
6
CMOS VLSI Design
SIMULATED NMOS I-V PLOT

180 nm TSMC process
BSIM 3v3 SPICE models
What differs?
250
Vgs = 1.8
200
Vgs = 1.5
150
Vgs = 1.2
Less ON current
No square law
Current increases
in saturation
Ids (mA)
100
Vgs = 0.9
50
Vgs = 0.6
0
0
0.3
0.6
0.9
1.2
1.5
Vds
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Slide
7
CMOS VLSI Design
VELOCITY SATURATION
We assumed carrier velocity is proportional to Efield
v = mElat = mVds/L
At high fields, this ceases to be true

Carriers scatter off atoms
Velocity reaches vsat
Electrons: 6-10 x 106 cm/s

Holes: 4-8 x 106 cm/s
nsat
nsat / 2
Better model
Elat
v
vsat Esat
Elat
1
Esat
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CMOS VLSI Design
slope = m
0
0
Esat
2Esat
3Esat
Elat
Slide
8
VEL SAT I-V EFFECTS
Ideal transistor ON current increases with VDD2

2
W Vgs Vt
I ds mCox
Vgs Vt
L
2
2
2
Velocity-saturated ON current increases with VDD

I ds CoxW Vgs Vt vmax
Real transistors are partially velocity saturated

Approximate with a-power law model
Ids VDDa
1 < a < 2 determined empirically
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Slide
9
CMOS VLSI Design
A-POWER
MODEL
Vgs Vt
cutoff
Vds Vdsat
linear
Vds Vdsat
saturation
I dsat Pc
400
Vt
gs
Vdsat Pv Vgs Vt
a /2
Simulated
a-law
Shockley
Ids (mA)
I ds I dsat ds
Vdsat
I dsat
300
Vgs = 1.8
200
Vgs = 1.5
100
Vgs = 1.2
Vgs = 0.9
Vgs = 0.6
0
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0.3
0.6
0.9
1.2
1.5
CMOS VLSI Design
1.8 V
ds
Slide
10
CHANNEL LENGTH MODULATION
Reverse-biased p-n junctions form a depletion region

Region between n and p with no carriers
Width of depletion Ld region grows with reverse bias
V
V
GND
Leff = L Ld
Source
Gate
Drain
DD
Shorter Leff gives more current
Ids increases with Vds

Even in saturation
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Depletion Region
Width: Ld
n+
L
Leff
n+
p GND
bulk Si
DD
Slide
11
CMOS VLSI Design
CHAN LENGTH MOD I-V
gs
Vt 1 lVds
2
400
Vgs = 1.8
300
Vgs = 1.5
200
Vgs = 1.2
100
0
0
I ds
Ids (mA)
Vgs = 0.9
Vgs = 0.6
0.3
0.6
0.9
1.2
1.5
1.8 Vds
l = channel length modulation coefficient

not feature size
Empirically fit to I-V characteristics
video.edhole.com
CMOS VLSI Design
Slide
12
BODY EFFECT
Vt: gate voltage necessary to invert channel
Increases if source voltage increases because
source is connected to the channel
Increase in Vt with Vs is called the body effect
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Slide
13
CMOS VLSI Design
BODY EFFECT MODEL

Vt Vt 0 g
fs = surface potential at threshold

fs 2vT ln
fs Vsb fs
NA
ni
Depends on doping level NA

And intrinsic carrier concentration ni
g = body effect coefficient

g
tox
ox
2q si N A
2q si N A
Cox
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Slide
14
CMOS VLSI Design
OFF TRANSISTOR BEHAVIOR

What about current in cutoff?
I
Simulated results
1 mA
What differs?
100 mA
Current doesnt go
to 0 in cutoff
10 mA
Saturation
Region
Subthreshold
Region
Vds = 1.8
1 mA
100 nA
10 nA
ds
Subthreshold
Slope
1 nA
100 pA
10 pA
Vt
0
0.3
0.6
0.9
1.2
1.5
1.8
Vgs
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Slide
15
CMOS VLSI Design
LEAKAGE SOURCES
Subthreshold conduction
Junction leakage
Gate leakage
Reverse-biased PN junction diode current

Tunneling through ultrathin gate dielectric
Transistors cant abruptly turn ON or OFF
Subthreshold leakage is the biggest source in

modern transistors
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Slide
16
CMOS VLSI Design
SUBTHRESHOLD LEAKAGE
Subthreshold leakage exponential with Vgs

Vgs Vt
I ds 0 vT2 e1.8
n is process dependent, typically 1.4-1.5
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I ds I ds 0e
nvT
Vds
v
1 e T
Slide
17
CMOS VLSI Design
DIBL
Drain-Induced Barrier Lowering
Vt Vt hVds
ttds
VVVh
High drain voltage causes subthreshold leakage to

________.
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Drain voltage also affect Vt
Slide
18
CMOS VLSI Design
DIBL
Drain-Induced Barrier Lowering
Vt Vt hVds
ttds
VVVh
High drain voltage causes subthreshold leakage to

increase.
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Drain voltage also affect Vt
Slide
19
CMOS VLSI Design
JUNCTION LEAKAGE
Reverse-biased p-n junctions have some leakage
Is depends
And area
VvD
T
I D I S e 1
on doping levels
and perimeter of diffusion regions

Typically < 1 fA/mm2
p+
n+
n+
p+
p+
n+
n well
p substrate
video.edhole.com
CMOS VLSI Design
Slide
20
GATE LEAKAGE
Carriers may tunnel thorough very thin gate oxides
Predicted tunneling current (from [Song01])
tox
VDD trend
0.6 nm
0.8 nm
JG (A/cm )
106
103
1.0 nm
1.2 nm
100
1.5 nm
109
1.9 nm
10-3
10-6
10-9
0
Negligible for older processes

May soon be critically important
video.edhole.com
CMOS VLSI Design
0.3
0.6
0.9
1.2
1.5
1.8
VDD
Slide
21
TEMPERATURE SENSITIVITY
Increasing temperature
ION
___________ with temperature

IOFF ___________ with temperature
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Reduces mobility
Reduces Vt
Slide
22
CMOS VLSI Design
TEMPERATURE SENSITIVITY
Increasing temperature
Reduces mobility
Reduces Vt
ION
decreases with temperature

IOFF increases with temperature
I ds
increasing
temperature
Vgs
video.edhole.com
Slide
23
CMOS VLSI Design
SO WHAT?
So what if transistors are not ideal?
But these effects matter for
Supply voltage choice

Logical effort
Quiescent power consumption
Pass transistors
Temperature of operation
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They still behave like switches.
Slide
24
CMOS VLSI Design
PARAMETER VARIATION
Transistors have uncertainty in parameters
Fast (F)
fast
FF
SF
Leff: ______
Vt: ______
tox: ______
pMOS
TT
FS
Slow (S): opposite

Not all parameters are independent
for nMOS and pMOS
video.edhole.com
Process: Leff, Vt, tox of nMOS and pMOS

Vary around typical (T) values
SS
slow
slow
nMOS
fast
Slide
25
CMOS VLSI Design
PARAMETER VARIATION
Transistors have uncertainty in parameters
Fast (F)
fast
FF
SF
Leff: short
Vt: low
tox: thin
pMOS
TT
FS
Slow (S): opposite

Not all parameters are independent
for nMOS and pMOS
video.edhole.com
Process: Leff, Vt, tox of nMOS and pMOS

Vary around typical (T) values
SS
slow
slow
nMOS
fast
Slide
26
CMOS VLSI Design
ENVIRONMENTAL VARIATION
VDD and T also vary in time and space
Fast:
Corner
Voltage
Temperature
1.8
70 C
VDD: ____
T: ____
F
T
S
video.edhole.com
Slide
27
CMOS VLSI Design
ENVIRONMENTAL VARIATION
VDD and T also vary in time and space
Fast:
Corner
Voltage
Temperature
1.98
0C
1.8
70 C
1.62
125 C
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VDD: high
T:
low
Slide
28
CMOS VLSI Design
PROCESS CORNERS
Process corners describe worst case variations
Describe corner with four letters (T, F, S)

nMOS speed
pMOS speed
Voltage
Temperature
video.edhole.com
If a design works in all corners, it will probably work for

any variation.
Slide
29
CMOS VLSI Design
IMPORTANT CORNERS
Some critical simulation corners include
nMOS
pMOS
VDD
Cycle time
Temp
Purpose
Power
Subthrehold
leakage
Pseudo-nMOS
video.edhole.com
Slide
30
CMOS VLSI Design
IMPORTANT CORNERS
Some critical simulation corners include
nMOS
pMOS
VDD
Temp
Cycle time
Power
Subthrehold
leakage
Pseudo-nMOS S
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Purpose
Slide
31
CMOS VLSI Design

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FREE VIDEO LECTURES FOR MBA

Harvey Mudd College

15: Nonideal Transistors

Process and Environmental Variations

IDEAL TRANSISTOR I-V

Shockley 1st order transistor models

CMOS VLSI Design

15: Nonideal Transistors

IDEAL NMOS I-V PLOT

15: Nonideal Transistors

SIMULATED NMOS I-V PLOT

15: Nonideal Transistors

SIMULATED NMOS I-V PLOT

15: Nonideal Transistors

We assumed carrier velocity is proportional to Efield

15: Nonideal Transistors

At high fields, this ceases to be true

Electrons: 6-10 x 106 cm/s

CMOS VLSI Design

VEL SAT I-V EFFECTS

Ideal transistor ON current increases with VDD2

Velocity-saturated ON current increases with VDD

15: Nonideal Transistors

Real transistors are partially velocity saturated

15: Nonideal Transistors

CMOS VLSI Design

CHANNEL LENGTH MODULATION

Reverse-biased p-n junctions form a depletion region

Shorter Leff gives more current

Ids increases with Vds

15: Nonideal Transistors

CHAN LENGTH MOD I-V

15: Nonideal Transistors

l = channel length modulation coefficient

CMOS VLSI Design

15: Nonideal Transistors

BODY EFFECT MODEL

fs = surface potential at threshold

Depends on doping level NA

15: Nonideal Transistors

g = body effect coefficient

OFF TRANSISTOR BEHAVIOR

15: Nonideal Transistors

Reverse-biased PN junction diode current

15: Nonideal Transistors

Transistors cant abruptly turn ON or OFF

Subthreshold leakage is the biggest source in

Subthreshold leakage exponential with Vgs

n is process dependent, typically 1.4-1.5

15: Nonideal Transistors

Drain-Induced Barrier Lowering

High drain voltage causes subthreshold leakage to

15: Nonideal Transistors

Drain voltage also affect Vt

Drain-Induced Barrier Lowering

High drain voltage causes subthreshold leakage to

15: Nonideal Transistors

Drain voltage also affect Vt