Scribd
Upload
54 views

Vil HDL (Ii) Verilog HDL (II)

The document provides examples of Verilog code for modeling digital logic circuits like flip-flops, counters, and full adders. It demonstrates using non-blocking assignments for sequential logic and blocking assignments for combinational logic. It also discusses using parameters to create reusable, configurable modules and generate blocks to instantiate variable numbers of modules or connections.

Uploaded by

Mohammad Seemab Aslam
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
54 views

Vil HDL (Ii) Verilog HDL (II)

The document provides examples of Verilog code for modeling digital logic circuits like flip-flops, counters, and full adders. It demonstrates using non-blocking assignments for sequential logic and blocking assignments for combinational logic. It also discusses using parameters to create reusable, configurable modules and generate blocks to instantiate variable numbers of modules or connections.

Uploaded by

Mohammad Seemab Aslam
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 23

V il HDL(II)

VerilogHDL(II)

//example 1.1
module ffNand;
wire
reg
nand #1

q, qBar;
preset, clear;
g1 (q, qBar, preset),
g2 (qBar, q, clear);

endmodule
d d l

//example 1.2
module ffNandSim;
wire
reg
nand
d #1

initial

g1 (q, qBar, preset),


g2 (qBar, q, clear);
begin

end
endmodule

q, qBar;
preset, clear;

//two slashes introduce a single line comment


$monitor ($time,,
"Preset = %b clear = %b q = %b qBar = %b",
preset clear
preset,
clear, q
q, qBar);
//waveform for simulating the nand flip flop
#10 preset = 0; clear = 1;
# 10 preset = 1;
# 10 clear = 0;
# 10 clear = 1;
# 10 $
$finish;;
3

//example 1.3
module m16 (value, clock, fifteen, altFifteen);
output
[3:0]
value;
output
fifteen,
altFifteen;
l Fif
input
clock;
dEd FF
dEdgeFF

a (value[0],
( l [0] clock,
l k ~value[0]),
l [0])
b (value[1], clock, value[1] ^ value[0]),
c (value[2], clock, value[2] ^ &value[1:0]),
d (value[3],
(value[3] clock,
clock value[3] ^ &value[2:0]);

assign fifteen = value[0] & value[1] & value[2] & value[3];


assign altFifteen = &value;
endmodule

//examples 3.2
3 2 and 1.4
14
module dEdgeFF (q, clock, data);
output
q;
reg
q;
input
clock, data;
initial
always

#10 q = 0;
(@negedge clock) #10 q = data;

endmodule

//example 1.6
module board;
wire
wire

m16
m555

[:]

count;
clock,
f,
af;

counter (count, clock, f, af);


clockGen (clock);

always @ (posedge clock)


$display ($time,,,"count=%d, f=%d, af=%d", count, f, af);
endmodule

//example 1.8
module m16Behav (value, clock, fifteen, altFifteen);
output
[3:0]
value;
reg
[3:0]
output
reg
input

value;
fifteen,
altFifteen;
fifteen,
altFifteen;
clock;

initial
value = 0;
always
begin
(@negedge clock) #10 value = value + 1;
if (value == 15)
begin
altFifteen = 1;
fifteen = 1;
end
else
begin
altFifteen = 0;
fifteen = 0;
end
end
endmodule
10

11

12

13

//example 4.1
module fullAdder(cOut, sum, aIn, bIn,
cIn);
output
cOut, sum;
input
aIn, bIn, cIn;
wire

x2;

nand

)x2, aIn, bIn),


)cOut, x2, x8);
)x9, x5, x6);
)x5, x1, x3),
)x1, aIn, bIn);
)x8, x1, x7);
)sum, x9),
) 3 x2),
)x3,
2)
)x6, x4),
)x4, cIn),
)x7 x6);
)x7,

xnor
nor
or
not

endmodule
14

15

16

Blockingvs.Nonblocking
Assignments
i

17

UseNonblockingforSequential
L i
Logic

18

UseBlockingforCombinational
L i
Logic

19

WhichAbstraction
istherightone?
Designersusuallyuseamixofallthree!Earlyonin
D
i

ll i f llth !E l i
thedesignprocesstheymightusemostly
behavioralmodels.Asthedesignisrefined,the
behavioralmodelsbegintobereplacedby
dataflowmodels.Finally,thedesignersuse
automatictoolstosynthesizealowlevelgatelevel
t
ti t l t th i l
l l t l l
model.

20

Example: Mixed Assignments


Example:MixedAssignments

21

W iti P
WritingParameterizedModels
t i dM d l

Parametersenablestaticconfigurationofmodulesat
instantiationtimeandcangreatlyincreasethe
usefulnessofyourmodules
22

GenerateBlocks
(Verilog2001)

Generateblockscanuse
parameterstoinstantiatea
variablenumberofsub
variablenumberofsub
modulesortocreatea
variablenumberofnets

23

You might also like