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Announcements: - Lab 1 Due in One Week

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Announcements: - Lab 1 Due in One Week

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Mohamed Rias

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Announcements

Lab 1 due in one week

CSE372
Digital Systems Organization and Design
Lab

Questions/comments?
Testbench coming soon (according to the TAs)

Todays lecture:
How FPGAs work

Prof. Milo Martin

Unit 2: Field Programmable Gate Arrays (FPGAs)

CSE 372 (Martin): FPGAs

Field Programmable Gate Array (FPGA)

CSE 372 (Martin): FPGAs

Early Programmable Logic Device

An alternative to a custom design

A high-end custom design mask set is expensive (millions of $!)

Advantages
Simplicity of gate-level design (no transistor-level design)
Fast time-to-market
No manufacturing delay
Can fix design errors over time (more like software)

Disadvantages
Expensive: unit cost is higher
Inefficient: slower and more power hungry

Result: good for low-volume or initial designs

CSE 372 (Martin): FPGAs

From UC-Berkeley CS152 slides

Modern FPGA: Xilinx Vertex II

For Comparison: FGPA vs Pentium 4

Not to scale
CSE 372 (Martin): FPGAs

CSE 372 (Martin): FPGAs

FPGA Design Flow

Review: Logical Completeness

Synthesis

AND, OR, NOT can implement ANY truth table

Break design into well-define logic blocks

Examples:
2-input gates
Only NANDs
Limited set of standard cells with three-inputs, one output

Place and route

Custom: position the devices and wires that connect them
FPGA: configure logic blocks and interconnect

Goals:
Reduce latency (performance)
Reduce area (cost)
Reduce power (performance and/or cost)
CSE 372 (Martin): FPGAs

Cin S

A B Cin

1. AND combinations
that yield a "1" in the
truth table
S

2. OR the results
of the AND gates

Mechanical process, but many optimizations

CSE 372 (Martin): FPGAs

Our Old Friend, The Full Adder

Add two bits and carry-in
produce one-bit sum and carry-out

An
Bn

A Better Full Adder

1
1

A B Cin S Cout

CarryInn
1

Add

!module full_adder(s, cout, a, b, cin);

output s, cout;
input a, b, cin;
CarryInn
xor (t1, a, b);
xor (s, t1, cin);
and (t2, t1, cin);
and (t3, a, b);
or (cout, t2, t3);
endmodule

CarryOutn

0 0

0 1

cin

1 0

a
b

1 1

An
Bn

Add
CarryOutn

t1
t2

cout
t3

CSE 372 (Martin): FPGAs

A Simple (Fake) FPGA Substrate

CSE 372 (Martin): FPGAs

How Do We Route Signals?

Switch matrix
Each junction has 6 switches
Each switch is a pass gate

Switch

Programming
Each pass gate controlled by 1-bit flip-flop
0/1 value of flip-flop set at configuration

Programmable interconnect

Pass Gate

Allows for arbitrary routing of signals

Each segment adds delay
Takes up lots of chip area

CSE 372 (Martin): FPGAs

More Wires

IBM

On-Chip Wires

IBM CMOS7, 6 layers of copper wiring

CSE 372 (Martin): FPGAs

Configure This As a Full Adder

A Better FPGA
Replace gates with general CLB

cin
a
b

Combinational logic block

s
cout

CSE 372 (Martin): FPGAs

CLB

CSE 372 (Martin): FPGAs

Combinational Logic Block

A Standard Xilinx CLB

Simple example CLB

Two 4-input LUTs

Any 4-input function
Limited 5-input functions

Configure as any two-input gate

Use 4-bit RAM to implement function
LUT - Lookup Table
Simple lookup operation

Two flip-flops
Fast carry logic (direct connect from adjacent CLBs)
LUTs can be be configured as RAM:
2x16 bit or 1x32 bit, single ported
1x16 bit dual ported

Add sequential state

Add a latch/flipflop or two

Routing
Short and long wires (skip some CLBs)
Clocks have dedicated wires

Also has IOBs (input/output blocks)

Specialized for off-chip signals, one per pin on package
CSE 372 (Martin): FPGAs

The Xilinx 4000 CLB

CSE 372 (Martin): FPGAs

Two 4-input functions, registered output

From UC-Berkeley CS150 slides

CSE 372 (Martin): FPGAs

From UC-Berkeley CS150 slides

5-input function, combinational output

CSE 372 (Martin): FPGAs

From UC-Berkeley CS150 slides

CLB Used as RAM

Fast Carry Logic

CSE 372 (Martin): FPGAs

From UC-Berkeley CS150 slides

Xilinx 4000 Interconnect

From UC-Berkeley CS150 slides

CSE 372 (Martin): FPGAs

From UC-Berkeley CS150 slides

Switch Matrix

CSE 372 (Martin): FPGAs

Xilinx 4000 Interconnect Details

From UC-Berkeley CS150 slides

CSE 372 (Martin): FPGAs

From UC-Berkeley CS150 slides

FPGA Design Issues

Our FPGAs: Virtex-2 Pro XC2VP30

How large should a CLB be?

Viertex-2 Pro

How many inputs?

How much logic and state?
Example: two full-adders plus two latches in each Xilinx CLB
N-bit counter uses N/2 CLBs

More powerful CLBs

More routing resources
Embedded PowerPC core

XC2VP30

Routing resources

Faster, better routing

Other imbedded hardware structures

RAM blocks
Multipliers
Processors
CSE 372 (Martin): FPGAs

30,816 CLBs
136 18-bit multipliers
2,448 Kbits of block RAM
Two PowerPC processors
400+ pins

CSE 372 (Martin): FPGAs

FPGA vs Custom Designs

Downside of configurability
Wires are much slower on FPGAs
Logic is much slower on FPGAs

However, FPGAs are real logic (not software)

Great for our prototyping

Synthesis to chip an option ($$$)

Standard cell design
Hard coded, but based on synthesis design flow
Not as good as full custom as used by Intel, AMD, IBM
Not to scale
CSE 372 (Martin): FPGAs

CSE 372 (Martin): FPGAs

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