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Lab 4: Implementing The I2C Wrapper With Write/Read Functionality

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45 views2 pages

Lab 4: Implementing The I2C Wrapper With Write/Read Functionality

Lab_Day3_PM

Uploaded by

Patrick Go
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Philippine Institute for Integrated Circuits

Rm. 413 UP NEC Building, Osmea Avenue, University of the Philippines Diliman, Quezon City, Philippines 1101
[email protected] (632) 9969293

Lab 4: Implementing the I2C Wrapper with


Write/Read Functionality
Introduction
For this lab exercise, you will implement the I2C wrapper from the ASM youve done in the
previous lab.

Implementation, Synthesis and Verification


1. You will still use the week2_lab_I2C directory for this exercise.
2. A new testbench is provided for this laboratory session. Modify the *.f file accordingly.
3. Make a copy of the I2C_master_writeonly.v and name it I2C_master_writeread.v. Edit the
new copy of the file to reflect the changes in the ASM youve finished in the previous
laboratory.
4. Verify the functionality of the RTL model. If successful, the output of simv should be as
shown below:
[rix@Runegrove sim]$ ./simv
Chronologic VCS simulator copyright 1991-2013
Contains Synopsys proprietary information.
Compiler version H-2013.06-SP1_Full64; Runtime version H-2013.06-SP1_Full64;
VCD+ Writer H-2013.06-SP1_Full64 Copyright (c) 1991-2013 by Synopsys Inc.
--- Transaction 01 ----- New Transaction --Flow: write
No error.
--- Transaction 02 ----- New Transaction --Flow: write
Error: yes
Reason: no ack
--- Transaction 03 ----- New Transaction --Flow: read
No error.
$finish called from file "tb_I2C_master_writeread.v", line 160.
$finish at simulation time
3110000
V C S
S i m u l a t i o n
R e p o r t
Time: 3110000 ps
CPU Time:
0.300 seconds;
Data structure size:
0.9Mb
Wed Apr 2 12:53:48 2014
[rix@Runegrove sim]$

5. The overall timing diagram and a zoom in on the read test case should look be like as
shown in Figure 1 and 2, respectively.

Page 1

Philippine Institute for Integrated Circuits


Rm. 413 UP NEC Building, Osmea Avenue, University of the Philippines Diliman, Quezon City, Philippines 1101
[email protected] (632) 9969293

Figure 1 Overview simulation results

Figure 2 First read test case simulation results

Synthesis and Verification


1. Upon successful verification of the RTL model, synthesize the design. Use the constraints
file provided.
2. Test whether the functionality of the synthesized design is still the same.
3. Add at least eight test cases in the testbench provided.

Page 2

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