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Testing of Vlsi Circuits

This document outlines the questions for the M.Tech II Semester Supplementary Examinations in Testing & Testability in April 2011. The exam is 3 hours long and covers topics related to VLSI systems, embedded systems, and VLSI design. Students must answer any 5 of the 8 questions provided, which cover topics such as modeling digital circuits, fault models, ATPG for sequential circuits, scan architectures, DFT approaches, signature analysis, self-test designs, memory testing, JTAG testing, and hazard detection.

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388 views

Testing of Vlsi Circuits

This document outlines the questions for the M.Tech II Semester Supplementary Examinations in Testing & Testability in April 2011. The exam is 3 hours long and covers topics related to VLSI systems, embedded systems, and VLSI design. Students must answer any 5 of the 8 questions provided, which cover topics such as modeling digital circuits, fault models, ATPG for sequential circuits, scan architectures, DFT approaches, signature analysis, self-test designs, memory testing, JTAG testing, and hazard detection.

Uploaded by

mittazj
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Code :9D55201

M.Tech II Semester Supplementary Examinations, April 2011


TESTING & TESTABILITY
(For students admitted in 2009-2010)
(Common to VLSI Systems,VLSI Systems Design, VLSI & VLSID, Embedded Systems)

Time: 3 hours

Max Marks: 60
Answer any FIVE questions
All questions carry equal marks

1. (a) Describe the concepts of modeling & digital circuits at logic level & register level.
(b) Explain any two delay models.
2. (a) Describe with the help of examples single struck & multiple struck fault models.
(b) Explain any two fault simulation applications.
3. (a) Explain ATPG for SSFs in sequential circuits.
(b) How do you select ATPG tool? Explain.
4. (a) With the help of neat block diagram, explain the scan Architectures & Testing.
(b) How do you perform generic boundary scan?
5. (a) Explain board level & system level DFT approaches.
(b) What is meant by signature analysis? Explain.
6. (a) Explain the advanced concept & design for self-test at board level.
(b) What is STUMPS? Describe.
7. (a) List & explain any two types of memories & integration.
(b) Explain the memory test architecture.
8. Write short notes on the following:
(a) JTAG testing feature.
(b) Hazard detection.
(c) RTS.

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