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Quartus II Introduction Verilog Design Using Megafunction: Alex Yang Northwestern Polytechnic University Fremont CA

The document describes using a megafunction in Quartus II to implement a finite impulse response (FIR) filter using Verilog. It involves: 1) Writing the Verilog code for the FIR filter with registers to store input samples. 2) Creating a multiplier megafunction module. 3) Instantiating the multiplier module in the FIR filter design to perform the multiplication operations between input samples and filter coefficients.

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39 views

Quartus II Introduction Verilog Design Using Megafunction: Alex Yang Northwestern Polytechnic University Fremont CA

The document describes using a megafunction in Quartus II to implement a finite impulse response (FIR) filter using Verilog. It involves: 1) Writing the Verilog code for the FIR filter with registers to store input samples. 2) Creating a multiplier megafunction module. 3) Instantiating the multiplier module in the FIR filter design to perform the multiplication operations between input samples and filter coefficients.

Uploaded by

sunilgurubaxani
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Quartus II Introduction

Verilog Design Using Megafunction













Alex Yang
Northwestern Polytechnic University
Fremont CA





I. Write the Verilog code first in Quartus II compiler

module FIRFilter(
x_i,
clk,
rst_i,
y_o
);
input[31:0] x_i;
input clk;
input rst_i;
output[31:0] y_o;

reg[31:0] xD1_r;
reg[31:0] xD2_r;
reg[31:0] xD3_r;
reg[31:0] xD4_r;

wire[31:0] y0_w;
wire[31:0] y1_w;
wire[31:0] y2_w;
wire[31:0] y3_w;
wire[31:0] y4_w;

parameter c0=32'h0000_0001;
parameter c1=32'h0000_0002;
parameter c2=32'h0000_0003;
parameter c3=32'h0000_0002;
parameter c4=32'h0000_0001;

always@(posedge clk)begin
if(rst_i)begin
xD1_r <= 32'h0000_0000;
xD2_r <= 32'h0000_0000;
xD3_r <= 32'h0000_0000;
xD4_r <= 32'h0000_0000;
end else begin
xD1_r <= x_i;
xD2_r <= xD1_r;
xD3_r <= xD2_r;
xD4_r <= xD3_r;
end
end
assign y_o=y0_w+y1_w+y2_w+y3_w+y4_w;
endmodule







II. Create Multiplier Module in Megafunction

- Click Tools -> MegaWizard Plug-In Manager


- Click Next


- Select LPM_MULT in Arithmetic, and type in Mult


- Click Next






- Click Next


- Click Next


- Click Next


- Click Next, Mult.v file is generated


- Click OK


III. Instantiate Mult module in your design

module FIRFilter(
x_i,
clk,
rst_i,
y_o
);
input[31:0] x_i;
input clk;
input rst_i;
output[31:0] y_o;

reg[31:0] xD1_r;
reg[31:0] xD2_r;
reg[31:0] xD3_r;
reg[31:0] xD4_r;

wire[31:0] y0_w;
wire[31:0] y1_w;
wire[31:0] y2_w;
wire[31:0] y3_w;
wire[31:0] y4_w;

parameter c0=32'h0000_0001;
parameter c1=32'h0000_0002;
parameter c2=32'h0000_0003;
parameter c3=32'h0000_0002;
parameter c4=32'h0000_0001;

always@(posedge clk)begin
if(rst_i)begin
xD1_r <= 32'h0000_0000;
xD2_r <= 32'h0000_0000;
xD3_r <= 32'h0000_0000;
xD4_r <= 32'h0000_0000;
end else begin
xD1_r <= x_i;
xD2_r <= xD1_r;
xD3_r <= xD2_r;
xD4_r <= xD3_r;
end
end
assign y_o=y0_w+y1_w+y2_w+y3_w+y4_w;

Mult uMult0(
.dataa(x_i),
.datab(c0),
.result(y0_w)
);
Mult uMult1(
.dataa(xD1_r),
.datab(c1),
.result(y1_w)
);
Mult uMult2(
.dataa(xD2_r),
.datab(c2),
.result(y2_w)
);
Mult uMult3(
.dataa(xD3_r),
.datab(c3),
.result(y3_w)
);
Mult uMult4(
.dataa(xD4_r),
.datab(c4),
.result(y4_w)
);
endmodule

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