Scribd
Upload
13K views

Moore Machine VHDL Code

This document describes a Moore finite state machine with 4 states (s0, s1, s2, s3) and 3 inputs (con1, con2, con3). The state transitions and outputs are defined by case statements. The current state is registered and the next state is determined based on the current state and inputs. The outputs are also determined by the current state.

Uploaded by

Kewl84
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
13K views

Moore Machine VHDL Code

This document describes a Moore finite state machine with 4 states (s0, s1, s2, s3) and 3 inputs (con1, con2, con3). The state transitions and outputs are defined by case statements. The current state is registered and the next state is determined based on the current state and inputs. The outputs are also determined by the current state.

Uploaded by

Kewl84
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
You are on page 1/ 2

library ieee;

use ieee.std_logic_1164.all;

entity test_state is
port ( clk : in std_ulogic;
reset : in std_ulogic;
con1, con2, con3 : in std_ulogic;
out1, out2 : out std_ulogic );
end test_state;

-------------------------------------------------------------------------------
-- MOORE machine (outputs come from CASE statment)
-------------------------------------------------------------------------------

architecture rtl of test_state is


type state_type is (s0, s1, s2, s3);
signal state, next_state : state_type;
begin -- rtl

state_encode : process ( state, con1, con2, con3 )


begin
next_state <= s1;
case state is
when s0 =>
next_state <= s1;
when s1 =>
if ( con1 = '1' ) then
next_state <= s2;
else
next_state <= s1;
end if;
when s2 =>
next_state <= s3;
when s3 =>
if ( con2 = '0' ) then
next_state <= s3;
elsif ( con3 = '0' ) then
next_state <= s2;
else
next_state <= s0;
end if;
end case;
end process state_encode;

state_register : process ( reset, clk )


begin
if ( reset = '0' ) then
state <= s0;
elsif ( clk'event and clk = '1' ) then
state <= next_state;
end if;
end process state_register;

state_decode : process ( state, con1, con2, con3 )


begin
case state is
when s0 =>
out1 <= '0';
out2 <= '0';
when s1 =>
out1 <= '1';
out2 <= '0';
when s2 =>
out1 <= '0';
out2 <= '1';
when s3 =>
if ( con2 = '0' ) then
out1 <= '0';
out2 <= '0';
elsif ( con3 = '0' ) then
out1 <= '0';
out2 <= '1';
else
out1 <= '1';
out2 <= '1';
end if;
end case;
end process state_decode;

end rtl;

You might also like