Design of a 22V32V-to-15V DC/DC Power

Converter under Input and Load Variations

Zheng Zhang
Department of Electrical Engineering and Computer Science, MIT
Email: z [email protected]
Submitted on May 16, 2012
AbstractThis report presents the design procedure of a buck
converter, which converts a 22V32V DC input voltage to a
15V DC output, under a resistive load variation from 1.5 to
4.5. Detailed analysis and simulation results, as well as electrical
and thermal device specications are provided. A voltage-mode
PI controller is designed to stabilize the averaged system under
input and load variations. The worst-case efciency of this buck
converter is above 94.59%.
I. DESIGN REQUIREMENTS
The design requirements of the electrical parameters for the
buck converter are listed in Table I.
TABLE I
DESIGN REQUIREMENTS.
Input voltage range 22 32 V
Input voltage transient limit 44 V for up to 1 ms
Output power range 50 150 V
Output voltage (static) 15 V3%
Output voltage (transient) 15 V20%
Output voltage ripple (p-p value) 100 mV
Input current ripple (p-p value, ideal source) 100 mA
Efciency 88%
Besides, it is required that the junction temperature of
the power devices should remain sufciently (at least 25

C)
below the allowable maximum junction temperature, while the
ambient temperature is in the range of 20

C +50

C. It is
also required that the temperature rise of inductor should be
below 50

C.
II. TOP-LEVEL DESIGN VIEW
As shown in Fig. 1, assume that the duty ratio of the switch
is d and the input DC voltage is V
1
, then the output DC voltage
can be decided as
V
o
= dV
1
. (1)
And the power at the output stage is
P
o
= V
2
o
/R
o
. (2)
Since V
o
= 15 V, and P
o
= 50 150 W, the load resistance
R
o
can vary in the range of 1.5 4.5. And accordingly, the
averaged current through the inductor shall vary in the range
of
10
3
10 A.
In our design, we see V
1
= 27 V and d =
5
9
as the nominal
design. The switching frequency is set as f
sw
= 200 KHz
based on the following tradeoffs:
V1
Ro
Lo
Co
+
-
Vo
S
D
+VD
-
I D
I s
ILo
q(t)
Fig. 1. Top-level schematic of a buck converter.
1) The switching frequency shall be high enough, since as
f
sw
gets higher the ripples in i
Lo
and v
o
become smaller;
2) The switching frequency cannot be arbitrarily high. As
f
sw
increases, the switching losses in the power devices
will increases. Meanwhile, the core power loss and loss
due to the skin effects also become more signicant as
f
sw
increases.
The following main problems need to be addressed in our
design:
1) The output stage should be designed such that the output
voltage has small ripples.
2) An input EMI lter should be added between the switch
and the input source, to ensure that the current owing
through the input source has small ripples.
3) The circuit should be designed such that this DC buck
converter can work well under load variations from 1.5
to 4.5 (or vise versa).
4) The power and passive devices and thermal devices
should be carefully selected such that designed circuit
works well under parasitic and thermal effects.
5) As the input voltage change in the range of 22 32 V,
the duty ratio d should be tuned according to the input
level to ensure V
o
stay at 15 V. This requires us to design
a feedback controller to form a stable close-loop system
such that the output stays at the nominal value.
III. CIRCUIT SCHEMATIC DESIGN
A. Output Stage
The output stage is designed under two constraints:
1) The inductor L
o
should be large enough to make the
current rippels of i
Lo
small enough;
t
T dT 2T
t 1 t 2
-0.5IL o,p-p
0.5ILo,p-p
i Lo,ac
Fig. 2. AC component of the current through inductor Lo.
V1
Ro
Lo
Co
+
-
Vo
S
D
+VD
-
ID
I s
ILo
q(t)
Rd
Cd
Cf
Lf
EMI
filter
Fig. 3. The buck converter with an EMI input lter.
2) The capacitor C
o
should be large enough to make the
voltage ripple of v
o
small enough.
Denote the voltage across the inductor L
o
as v
Lo
. When
the switch turns on V
D
= V
1
and v
Lo
= V
1
V
o
= V
1
15;
otherwise, the diode turns on and v
Lo
= 15 V. Therefore,
the peak-to-peak current of L
o
can be computed as
I
Lo,pp
=
1
L
o
(V
1
15) dT =
1
L
o
(V
1
15)
15
V
1
T, (3)
which approaches the maximum (worst-case) value when V
1
=
32V. To ensure the peak-to-peak value of the inductor current
below a specied bound
1
, the inductor value should be
L
o

15
225
32

1
=
39.8438

1
H. (4)
Here we choose
1
= 1.4A, then we have
L
o
28.46 H. (5)
The ac component of i
Lo
is shown in Fig. 2. Assume that
capacitor C
o
is large enough, and this ac current all ows
through C
o
, the output voltage ripple (peak-to-peak value) can
be computed as
V
o,pp
=
1
C
o

t2
t1
i
L,ac
dt =
I
L,pp
T
8C
o
, (6)
Given an upper bound
2
for V
o,pp
, the capacitance should
be selected according to
C
o

I
L,pp
T
8
2
. (7)
Since it is required that V
o,pp
1 mV, we can select
2
= 0.1
V and lead to
C
o
3.5 F. (8)
is,ac
Rd
Cd
Cf
Lf
ix
t
T dT
is,ac
(1-d)I Lo
-dI Lo
Fig. 4. Left: the ac signal model to analyze input current ripple. Right:
waveform of the ac component of the switch current.
Our simulation results show that when we increases C
o
and decreases L
o
, the maximum transient magnitude of V
o
would decrease. Based on this observation, we remarkably
increase C
o
and slightly increase L
o
which leads to smaller
inductor current ripples, much smaller output voltage ripples
and much smaller transient peak of v
o
. Based on the data sheet
information, we select
C
o
= 100 F, L
o
= 31.5 H. (9)
B. Input-Stage EMI Filter
To reduce the current ripples of the input stage, we can
add a damped LC lter, as shown in Fig. 3. Since the switch
current i
s
(t) I
Lo
when the switch turns on and i
s
(t) = 0
when the switch turns off, we can model the output stage by
a current source and get an equivalent circuit for analyzing
the input current of this converter, as shown in the left part of
Fig. 4. The input current of this circuit model is in fact the
ac component of the switch current, the waveform of which
is plotted in the right part of Fig. 4.
To reduce the ripple of the input current, we need to reduce
its ac component i
x
. For simplicity, we perform the ac analysis
using V
1
=30 and d = 0.5, since in this case the ac component
of i
s,ac
is odd in time and its n-th Fourier coefcient can be
easily obtained as
I
n
s,ac
=
2I
L
n
. (10)
We only consider the fundamental harmonic, since the higher-
order harmonics in the input current are negligible due to the
low-pass property of the damped EMI lter. In Laplace domain
i
x
(s) = g(s)i
s,ac
(s), (11)
where g(s) is the transfer function from switch current to input
current. We can select a large damping capacitor C
d
such that
2f
sw
C
d
1/R
d
, and thus
g(s)
i
x
(s)
i
s,ac
(s)
=
1
s
2
L
f
C
f
+s
L
f
R
d
+ 1
(12)
in the frequency band of interest. We notice that when s = 0,
20lg|g(s)| = 0, and |g(s)| decreases by 40 dB/Dec when >
1

C
f
L
f
.
There is a negative resistance under constant power trans-
fer (seen from the switch), which is calculated as
r
l
=
P
o
I
2
in
=
V
2
1
P
o
, . (13)
10
2
10
0
10
2
10
4
10
6
10
8
10
10
150
100
50
0
(rad/sec)
2
0
l
g
(
|
g
(
j

)
|
)
Fig. 5. Magnitude of the transfer function g(s) (current gain of the EMI
lter).
Fig. 6. Circuit schematic used for simulation of the steady-state and transient
behavior of Vo.
The minimum value of |r
l
| is 3.2267 when V
1
= 22 V. To
make the EMI lter well damped, R
d
should be adequately
below 3.2267. In our design, we select R
d
= 0.4. To make
2f
sw
C
d
1/R
d
, we select C
d
= 3.3 mF.
We consider the worst case: I
Lo
= 10 A, which occurs
when the output power is 150 W. In this case, the magnitude
of the fundamental component of i
s,ac
is
i
1
s,ac
=
2I
Lo

sin(2f
sw
t) = 6.3662sin(2f
sw
t). (14)
To make the ripple of the input current below
3
= 100 mA,
we can select L
f
and C
f
such that
40

lg (2f
sw
) lg

C
f
L
f

20

lg (6.3662) lg

3
2

(15)
from which we get
1

C
f
L
f
1.113 10
5
rad/ sec . (16)
To be on the safe side, we select C
f
= 20F and L
f
= 9
H, which leads to
1

C
f
L
f
= 7.45 10
4
rad/sec.
With C
f
= 20F, L
f
= 9H, C
d
= 3.3mF and R
d
= 0.4,
the magnitude of g(s) is plotted in Fig. 5. Clearly, this EMI
lter is a well-damped low-pass lter. At f
sw
= 20 KHz, |g(s)|
is 49 dB, and thus the ac component of the switch current
can be well ltered, leading to very small ripples in the input
current.
Fig. 7. Transient behavior of the output voltage, showing the transient limit.
Fig. 8. Steady-state waveform of the output voltage, showing the worst-case
voltage ripple.
C. Simulation Results
Using the above specied design parameters, we set V
1
=
32 V and d = 0.4688 to check the transient and steady-state
waveforms of V
o
. The circuit schematic used for simulation
is shown in Fig. 6. In this simulation, the load is rst set as
1.5, and then it was changed to 4.5.
1) Output Voltage: As shown in Fig. 7, during the steps
between the minimum and maximum load, the maximum
output voltage is about 17.8 V. The steady-state waveform
of V
o
is plotted in Fig. 8, which shows that V
o,pp
= 8.1 mV
and the average value is 14.735 V.
2) Input Current: To see the worst-case input current ripple,
we set the input voltage as 22 V, R
o
= 1.5 and d = 0.6818.
As shown in Fig. 9, the worst-case peak-to-peak value is 27
mA.
Fig. 9. Steady-state waveform of the input current, showing the worst-case
ripples.
3) Output Power: Fig. 10 shows the transient behavior of
the current through I
Lo
. Clearly, when the load is 1.5, the
averaged value is 10 A, leading to 150-W output power. When
the load is 4.5, the averaged value is 3.33 A, delivering 50-
W power to the load. The maximum peak-to-peak current of
this inductor is 1.2 A when V
1
= 32 V.
Fig. 10. Transient behavior of the current through output-stage inductor Lo,
showing the output power range.
4) Summary: The simulated performance parameters are
summarized in Table II. Clearly, the listed electrical parameters
all meet the corresponding design requirements.
TABLE II
SIMULATION RESULTS OF THE PROPOSED DESIGN.
Switching frequency 200 KHz
Input voltage range 22 32 V
Output power range 50 150 V
Output voltage (static) 15 V1.67%
Maximum output voltage (transient) 17.8 V (+18.67%)
Maximum output voltage ripple (p-p value) 8.1 mV
Maximum input current ripple (p-p value) 27 mA
IV. ELECTRICAL AND THERMAL DEVICE SELECTION
A. Switch and Diode
1) Switch: The worst-case conduction loss of the switch is
P
sw,on
= dI
2
Lo
R
ds
= d

P
o
V
o

2
R
ds
. (17)
where R
ds
is the drain-to-source resistance at the maximum
allowable junction temperature.
The switching loss can be calculated as the sum of the loss
during the rise and fall time. Since the maximum drain-to-
source voltage is V
1
and the maximum current is I
Lo
=
Po
Vo
,
the switching loss is
P
sw,rf
=
1
2
V
1
P
o
V
o
(t
r
+t
f
) f
sw
=
P
o
2d
(t
r
+t
f
) f
sw
. (18)
To make the total loss small, we should select a switch
that has small conduction resistance and small rise/fall time.
In our design, IRFZ48N Power MOSFET is selected due to
the good tradeoff between R
ds
and t
r
+t
f
. At the maximum
allowable temperature 175

C, the drain-to-source resistance is

R
ds
= 0.014 2.3 = 0.0322 . (19)
Clearly shown in (17) and (18), the worst-case power loss
happens when P
o
= 150 W. With t
r
= 78 ns and t
f
=
34ns, the worst-case conduction loss, switching loss and total
loss are plotted in Fig. 11 as functions of the duty ratio. The
simulation results in Fig. 11 show that the maximum worst-
case switch device loss is
P
sw,worstcase
= max (P
sw,on
+P
sw,rf
) = 5.0934 W, (20)
which occurs when d =
15
32
.
0.45 0.5 0.55 0.6 0.65 0.7
1
2
3
4
5
6
d (duty ratio)
m
a
x
i
m
u
m

w
o
r
s
t

c
a
s
e

p
o
w
e
r

l
o
s
s


conduction loss
switching loss
total loss
Fig. 11. Loss of the IRFZ48N Power MOSFET under different duty ratios.
2) Diode: Since the maximum reverse voltage is 32 V
and the maximum forward current can be 10 A, we select
30CPQ45 as our diode device. The conduction loss is
P
d,on
= I
Lo
(1 d)V
F
=
P
o
V
o
(1 d)V
F
, (21)
where V
F
is the forward voltage at the maximum allowable
junction temperature. Clearly, the worst-case conduction loss is
obtained when P
o
= 150W and d =
15
32
. In this case I
Lo
= 10
A and V
F
= 0.4 F, leading to the worst-case conduction loss
max (P
d,on
) = 2.12 W. (22)
The worst-case discharge loss due to the diode capacitance
can be calculated as
P
d,cap
= f
sw

32
0
CV dV 0.40 W (23)
which is very small compared with the conduction loss.
Therefore, the worst-case diode power loss is
P
d,worstcase
= max (P
d,on
) +P
d,cap
= 2.52 W. (24)
B. Passive Components: Capacitors
1) C
f
: The simulation results show that the current through
C
f
can approach 7 A, therefore use the 20-F CS4 capacitor
for the LC lter. The parasitic resistance of this capacitor is
2.5 m and the parasitic inductance is 11 nH.
2) C
d
: The maximum voltage across C
d
is around 32 V
(when V
1
= 32 V), and the maximum current can be around
0.6 A, therefore we use the 3.3-mF U767D capacitor. The
parasitic resistance of this capacitor is about 11 m, which is
negligible compared with the damping resistor.
3) C
o
: Simulation results show that the peak-to-peak cur-
rent of this capacitor is around 0.6 A and the averaged current
is 0. Since V
o
= 15 V, we select the 100-F HD-series
capacitor, which allows the simulated capacitor current.
C. Passive Components: Inductors
1) L
f
: The maximum input current is
I
in,max
=
max (P
o
)
min V
1
)
= 6.82 A. (25)
There is a constraint for the wire area A
wire
by the maximum
current density:
I
in,max
A
wire
500 A/cm
2
. (26)
The second constraint is that the maximum ux density B
max
should be below the saturated ux density B
sat
, i.e.,
B
max
=
L
f
I
in,max
NA
c
< B
max
(27)
where N is the turn number, A
c
is the effective core area.
Based on these two constraints, we select the RM10/I core
set, with A
L
= 250 nH and N = 6. The diameter of the wire
(size-13 copper wire) is
d
wire
= 1.83 mm. (28)
The wire resistance of the inductor is
R
Lf
= N l
turn

cu,wire
= 2.49 m (29)
where l
turn
= 52 mm is the average length of turn, and

cu,wire
= 7.9910
3
/m is the resistivity of size-13 copper
wire.
2) L
o
: The output-stage inductor L
o
can be designed in a
similar way. For this inductor, we use the RM12/I core set,
with A
L
= 315 nH and N = 10. We use the size-14 copper
wire (diameter is 1.63 mm). The resulting wire resistance is
R
Lo
= N l
turn

cu,wire
= 6.161 m. (30)
3) Power Loss of Inductors: The inductor loss includes the
winding and core loss. The winding loss of inductor L
f
is
P
Lf,winding
= I
2
Lf
R
Lf
=

P
o
V
1

2
R
Lf
. (31)
When P
o
= 150 W and V
1
= 22 V, we have the worst-case
winding loss for L
f
:
max (P
Lf,winding
) = 6.82
2
0.00249 = 0.1158 W. (32)
For the inductor L
f
, we have C
M
= 2.510
4
, f
sw
= 210
5
Hz, = 1.63, = 2.45, B
ac,peak
2.2282 10
3
T, and
V
core
= 4.31cm
3
, therefore, the core loss can be decided as
P
Lf,core
= C
M
f
2
sw
(B
ac,peak
)

V
core
= 0.15 mW, (33)
which is much smaller than the winding loss. Therefore, the
worst-case loss of L
f
is
P
Lf,worstcase
= max (P
Lf,winding
) +P
Lf,core
= 0.116 W.
(34)
Similarly, for the output-stage inductor L
o
the maximum
winding loss can be calculated as
max (P
Lo,winding
) = 10
2
0.006161 = 0.6161 W. (35)
The core loss is
P
Lo,core
= C
M
f
2
sw
(B
ac,peak
)

V
core
= 7.80 mW. (36)
THE worst-case loss of L
o
is
P
Lo,worstcase
= max (P
Lf,winding
) +P
Lf,core
= 0.6239 W.
(37)
4) Temperature Rise of Inductors: For the inductor L
f
, the
maximum temperature rise is
T
Lf,max
= P
Lf,worstcase
Z
,RM10
= 3.48

C. (38)
The maximum temperature rise for the inductor L
o
is
T
Lo,max
= P
Lo,worstcase
Z
,RM12
= 14.35

C. (39)
D. Heat Sinks
The junction temperature of a power device can be ex-
pressed as a function of the power dissipation P
diss
, ambient
temperature T
A
, junction-to-case thermal resistance R
,JC
,
case-to-sink thermal resistance R
,CS
and sink-to-ambient
thermal resistance R
,SA
:
T
J
= T
A
+P
diss
(R
,JC
+R
,CS
+R
,SA
) . (40)
Since our design should work for the worst case, we assume
that T
A
= 50

C, and we require the junction temperature is at

least 25

C below the maximum allowable temperature at the

device junction specied by the data sheet.
1) Heat Sink for the Switch: For the IRFZ48N Power
MOSFET, the calculated worst-case device loss is 5.0943
W. From the data sheet we have R
,JC
= 1.15

C/W,
R
,CS
= 0.50

C/W, and the specied maximum allowable

junction temperature is 175

C, therefore, the heat sink thermal

resistance should be
R
,SA

175 25 50
5.0943
1.15 0.5 = 17.98

C/W. (41)
Therefore, we have many choices for the heat sink. In our
design, we select ML73/1.5 as the heat sink, the thermal
resistance of which is 11.0

C/W.
2) Heat Sink for the Diode: For the 30CPQ45 Schot-
tky Diode, the calculated worst-case power loss is 2.52
W. From the data sheet we have R
,JC
= 1.10

C/W,
R
,CS
= 0.24

C/W, and the specied maximum allowable

junction temperature is 150

C, therefore, the heat sink thermal

resistance should be
R
,SA

150 25 50
2.52
1.10 0.24 = 28.42

C/W.
(42)
Therefore, we have many choices for the heat sink. In our
design, we use ML24 to remove the heat of the diode, the
thermal resistance of which is 16.7

C/W.
E. Power Efciency
The power efciency can be estimated as
=
P
o
P
o
+P
loss
(43)
where P
loss
is the total power loss which can be calculated as
P
loss
= P
sw,on
+P
sw,rf
+P
d,on
+P
d,cap
+P
Lf,winding
+
P
Lf,core
+P
Lo,winding
+P
Lo,core
.
(44)
In our estimation, we use the worst-case capacitance discharge
loss (i.e., 0.40 W) for P
d,cap
. According to (17), (18), (21),(31)
and (35), we know that the power efciency depends on the
duty ratio d and output power P
o
. Fig. 12 has plotted as a
function of d and P
o
. From the simulation results we know
that the minimum power efciency is

min
= 94.59%. (45)
Note that the practical minimum power efciency can be
larger, since in our calculation the worst-case P
d,cap
is used.
Fig. 12. Power efciency of the buck converter under different duty ratio
and output power values.
3000 2500 2000 1500 1000 500
2
1
0
1
2
x 10
4
real
i
m
a
g


p
1
p
2
p
3
Fig. 13. The voltage-mode controlled system is stable, since the real part of
its poles are all negative for any Ro [1.5, 4.5].
V. FEEDBACK CONTROL
This section designs a voltage-model feedback controller for
the buck converter such that:
1) The averaged output voltage can stay at 15 V when there
is a step change in the input voltage;
2) The closed-loop system is stable when the load resistor
varies in the range of 1.5 4.5.
A. State-Space Model
From Fig. 1, we can set up a state-space model for the buck
converter:
L
o
diLo
dt
= q(t)v
1
v
o
(t)
C
o
dvo
dt
= i
Lo
(t)
vo(t)
Ro
.
(46)
Averaging the above state-space model we have
L
o
diLo
dt
=

dv
1
v
o
C
o
dvo
dt
= i
Lo

vo
Ro
(47)
where

d = q(t).
At the nominal point, we have v
o
= V
o
= 15 V, v
1
= V
1
=
27V , i
Lo
= I
Lo
=
Vo
Ro
,

d = D =
Vo
V1
=
15
27
, and the left-hand
side of (47) is zero. Now assume that the system is perturbed
away from the equilibrium point: v
1
= V
1
+ v
1
,

d = D +

d,
v
o
= V
o
+ v
o
and i
Lo
= I
Lo
+

i
L
. By linearizing (47), we
obtained the linearized model:
d

iLo
dt
=
1
Lo

D v
1
+V
1

d v
o

d vo
dt
=
1
Co

i
Lo

vo
Ro

.
(48)
In Laplace domain we have

s
2
L
o
C
o
+s
L
o
R
o
+ 1

v
o
(s) = D v
1
(s) +V
1

d(s), (49)
from which we get two transfer functions
H
1
(s) =
v
o
(s)
v
1
(s)
=
D

s
2
L
o
C
o
+s
Lo
Ro
+ 1
(50)
and
H
2
(s) =
v
o
(s)

d(s)
=
V
1

s
2
L
o
C
o
+s
Lo
Ro
+ 1
. (51)
B. PI Controller Design
We need to design a PI controller (of course we can also
use a PID controller)
K(s) = a
1
+
a
2
s
, (52)
such that

d(s) = K(s) ( v
o
(s) v
ref
(s)) , (53)
and the close-loop system is stable and its step response y(t)
approaches 0 as t . Since we want v
o
(s) = 0, we set
v
ref
= 0. Substitute (53) into (49) we get the transfer function
of the close-loop system:
G(s) =
sD

s
3
L
o
C
o
+s
2
Lo
Ro
+s (1 V
1
a
1
) V
1
a
2
. (54)
From (54) we know that due to the integrator in the
controller, the step response y(t) is zero when t since
G(0) = 0. If the system is stable, its poles p
1
, p
2
, p
3
C

,
which leads to
1 V
1
a
1
> 0 and V
1
a
2
< 0. (55)
Therefore, we should select a
1
and a
2
such that a
1
is small
and a
2
< 0 to make the system stable for R
o
[1.5, 4.5].
A simple MATLAB experiment shows that if we select a
1
=
0.008 and a
2
= 20, the system is stable under load variation.
To see this, the three poles are plotted in Fig. 13 as the load
resistor R
o
changes from 1.5 to 4.5. Clearly, under load
variations all poles are located on the left-hand rise (LHS) of
the complex plane, thus the close-loop system is guaranteed
stable.
C. Results
1) Whole System Structure: The block diagram of the buck
converter with the voltage-mode PI controller is given in
Fig. 14. The block diagram includes the following blocks
H
1
(s), the signal path from v
1
(s) to v
o
(s), marked in
black;
H
2
(s), the signal path from the controlled duty ratio

d(s)
to v
o
(s) marked in blue;
K(s), the PI controller block which transfers the output
offset to the control signal

d(s), hilighted in red.
TABLE III
DEVICE SUMMARY.
Devices Component Selection Remarks
Switch IRFZ48N MOSFET worst-case loss 5.0934 W, break-down V
DS
55V
Diode 30CPQ45 Schottky Diode worst-case loss 2.52 W, max. reverse voltage 45 V
R
d
(resistor in the damping leg of the EMI lter) 0.4
C
f
(capacitor for the input lter) CSZ 20.0F parasitic resistance 0.0025, parasitic inductance 11 nH
C
d
(capacitor for the damping leg in EMI lter) U767D 3.3 mF parasitic resistance 0.011
Co (capacitor at output stage) HD Series 100F parasitic resistance 0.074
L
f
(inductor for EMI lter) 9H, RM10/I core A
L
= 250 nH, turn # 6, size-13 copper wire (diameter: 1.83 mm),
wire resistance 2.49m, max. loss 0.116 W, temperature rise 3.48

C
Lo (inductor at output stage) 31.5H, RM12/I core A
L
= 315 nH, turn # 10, size-14 copper wire (diameter: 1.68 mm),
wire resistance 6.161m, max. loss 0.6239 W, temperature rise 14.35

C
Heat sink for MOSFET switch ML73/1.5 R

= 11.0

C/W
Heat sink for diode ML24 R

= 16.7

C/W
Fig. 14. MATLAB Simulink model of the whole buck converter with voltage-
mode PI controller.
0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1
1
0
1
2
3
4
5
6
time (s)
$
\
h
a
t

v
_
o
$
Fig. 15. Time-domain response when the input steps from 27 V to 32 V.
The y-axis data means vo(t), the deviation of the averaged output from the
desired value 15 V, which decays to 0 within 0.01 second.
2) Simulation Result: We use a step input of magnitude 5V
to perform the time-domain simulation, which means a step of
the DC input from the nominal value 27 V to the maximum
value 32V. Clearly shown in Fig. 15, under the input step the
offset of the averaged output decays to zero (and v
o
returns
to the desired value V
o
= 15V) within 0.01 second.
VI. SUMMARY
A. Device Selection Summary
The electrical and thermal devices, including their parasitic
effects, power loss and temperature rise are summarized in
Table III.
Fig. 16. The nalized circuit that includes parasitic effects.
B. Performance Summary
Now we include device parasitics (as shown in Fig. 16) to
redo the simulation. The simulation results are summarized in
Table IV. Since the break-down drain-to-source voltage of the
selected IRFZ48N MOSFET is 55 V, and the the maximum
reverse voltage of the selected 30CPQ45 Schottky Diode is
45 V, this circuit can survive under 44-V input transient limit.
Clearly, the results are very close the our previous design, and
all design specications are satised.
TABLE IV
SIMULATION RESULTS OF THE PROPOSED DESIGN, INCLUDING PARASITIC
EFFECTS.
Switching frequency 200 KHz
Input voltage range 22 32 V
Tolerate 44-V input transient limit? yes
Output power range 50 150 V
Output voltage (static) 15 V1.33%
Maximum output voltage (transient) 17.75 V (+18.33%)
Maximum output voltage ripple (p-p value) 9 mV
Maximum input current ripple (p-p value) 31 mA
Minimum efciency > 94.59%