This document describes a processor architecture with the following key components:
- Registers to store data values (R0, R1, R2, R3)
- A counter to track the instruction count
- Decoders to extract control signals from the instruction and counter values
- An ALU to perform arithmetic/logic operations on register values
- Tri-state buffers to control data movement to/from the shared bus
The design uses a clock, reset and control signals to sequence data through the registers and ALU each cycle to execute instructions.
This document describes a processor architecture with the following key components:
- Registers to store data values (R0, R1, R2, R3)
- A counter to track the instruction count
- Decoders to extract control signals from the instruction and counter values
- An ALU to perform arithmetic/logic operations on register values
- Tri-state buffers to control data movement to/from the shared bus
The design uses a clock, reset and control signals to sequence data through the registers and ALU each cycle to execute instructions.
This document describes a processor architecture with the following key components:
- Registers to store data values (R0, R1, R2, R3)
- A counter to track the instruction count
- Decoders to extract control signals from the instruction and counter values
- An ALU to perform arithmetic/logic operations on register values
- Tri-state buffers to control data movement to/from the shared bus
The design uses a clock, reset and control signals to sequence data through the registers and ALU each cycle to execute instructions.
This document describes a processor architecture with the following key components:
- Registers to store data values (R0, R1, R2, R3)
- A counter to track the instruction count
- Decoders to extract control signals from the instruction and counter values
- An ALU to perform arithmetic/logic operations on register values
- Tri-state buffers to control data movement to/from the shared bus
The design uses a clock, reset and control signals to sequence data through the registers and ALU each cycle to execute instructions.
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Contador:
Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_signed.all; Use work.subccts.all;
Entity proc IS Port (Data :IN STD_LOGIC_VECTOR(7 DOWNTO 0); Reset, w :IN STD_LOGIC; Clock :IN std_LOGIC; F, Rx, Ry :IN STD_LOGIC_VECTOR(1 DOWNTO 0); Done :BUFFER STD_LOGIC; BusWires :INOUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END proc;
ARCHITECTURE Behavior OF proc IS SIGNAL Rin, Rout : STD_LOGIC_VECTOR(0 TO 3); SIGNAL Clear, High, AddSub : STD_LOGIC; SIGNAL Extern, Ain, Gin, Gout, FRin : STD_LOGIC; SIGNAL Count, Zero : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL T, I, X, Y : STD_LOGIC_VECTOR(0 TO 3); SIGNAL R0, R1, R2, R3 : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL A,Sum,G : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL Func, FuncReg : STD_LOGIC_VECTOR(1 TO 6);
Begin Zero <= "00" ; High <= '1'; Clear <= Reset OR Done OR (NOT w AND T (0)); counter: upcount PORT MAP (Clear, Clock, Count); decT: dec2to4 PORT MAP (Count, High, T); Func <= F & Rx & Ry; FRin <= w AND T(0); functionreg: regn GENERIC MAP (N => 6) PORT MAP (Func, FRin, Clock, FuncReg); decI: dec2to4 PORT MAP (FuncReg(1 To 2), High, I); decX: dec2to4 PORT MAP (FuncReg(3 To 4), High, X); decY: dec2to4 PORT MAP (FuncReg(5 To 6), High, Y); Extern <= I(0) AND T(1); Done <= ((I(0) OR I(1))AND T(1)) OR ((I(2) OR I(3)) AND T(3)); Ain <= (I(2) OR I(3)) AND T(1); Gin <= (I(2) OR I(3)) AND T(2); Gout <= (I(2) OR I(3)) AND T(3); AddSub <= I(3); RegCntl: For k IN 0 TO 3 GENERATE Rin(k) <= ((I(0) OR I(1)) AND T(1) AND X(k)) OR ((I(2) OR I(3)) AND T(3) AND X(k)); Rout(k) <= (I(1) AND T(1) AND Y(k)) OR ((I(2) OR I(3)) AND ((T(1) AND X(k)) OR (T(2) AND Y(k)))); END GENERATE RegCntl; tri_extern: trin PORT MAP (Data, Extern, BusWires); reg0: regn PORT MAP (BusWires, Rin(0), Clock, R0); reg1: regn PORT MAP (BusWires, Rin(1), Clock, R1); reg2: regn PORT MAP (BusWires, Rin(2), Clock, R2); reg3: regn PORT MAP (BusWires, Rin(3), Clock, R3); tri0: trin PORT MAP (R0, Rout(0), BusWires); tri1: trin PORT MAP (R1, Rout(1), BusWires); tri2: trin PORT MAP (R2, Rout(2), BusWires); tri3: trin PORT MAP (R3, Rout(3), BusWires); regA: regn PORT MAP (BusWires, Ain, Clock, A); alu: WITH AddSub SELECT Sum <= A+BusWires WHEN '0', A-BusWires WHEN OTHERS; regG: regn PORT MAP (Sum, Gin, Clock, G); triG: trin PORT MAP (G, Gout, BusWires); END Behavior;
Procesador: Library ieee; Use ieee.std_logic_1164.all; Use ieee.std_logic_signed.all; Use work.subccts.all;
Entity proc IS Port (Data :IN STD_LOGIC_VECTOR(7 DOWNTO 0); Reset, w :IN STD_LOGIC; Clock :IN std_LOGIC; F, Rx, Ry :IN STD_LOGIC_VECTOR(1 DOWNTO 0); Done :BUFFER STD_LOGIC; BusWires :INOUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END proc;
ARCHITECTURE Behavior OF proc IS SIGNAL Rin, Rout : STD_LOGIC_VECTOR(0 TO 3); SIGNAL Clear, High, AddSub : STD_LOGIC; SIGNAL Extern, Ain, Gin, Gout, FRin : STD_LOGIC; SIGNAL Count, Zero : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL T, I, X, Y : STD_LOGIC_VECTOR(0 TO 3); SIGNAL R0, R1, R2, R3 : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL A,Sum,G : STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL Func, FuncReg : STD_LOGIC_VECTOR(1 TO 6);
Begin Zero <= "00" ; High <= '1'; Clear <= Reset OR Done OR (NOT w AND T (0)); counter: upcount PORT MAP (Clear, Clock, Count); decT: dec2to4 PORT MAP (Count, High, T); Func <= F & Rx & Ry; FRin <= w AND T(0); functionreg: regn GENERIC MAP (N => 6) PORT MAP (Func, FRin, Clock, FuncReg); decI: dec2to4 PORT MAP (FuncReg(1 To 2), High, I); decX: dec2to4 PORT MAP (FuncReg(3 To 4), High, X); decY: dec2to4 PORT MAP (FuncReg(5 To 6), High, Y); Extern <= I(0) AND T(1); Done <= ((I(0) OR I(1))AND T(1)) OR ((I(2) OR I(3)) AND T(3)); Ain <= (I(2) OR I(3)) AND T(1); Gin <= (I(2) OR I(3)) AND T(2); Gout <= (I(2) OR I(3)) AND T(3); AddSub <= I(3); RegCntl: For k IN 0 TO 3 GENERATE Rin(k) <= ((I(0) OR I(1)) AND T(1) AND X(k)) OR ((I(2) OR I(3)) AND T(3) AND X(k)); Rout(k) <= (I(1) AND T(1) AND Y(k)) OR ((I(2) OR I(3)) AND ((T(1) AND X(k)) OR (T(2) AND Y(k)))); END GENERATE RegCntl; tri_extern: trin PORT MAP (Data, Extern, BusWires); reg0: regn PORT MAP (BusWires, Rin(0), Clock, R0); reg1: regn PORT MAP (BusWires, Rin(1), Clock, R1); reg2: regn PORT MAP (BusWires, Rin(2), Clock, R2); reg3: regn PORT MAP (BusWires, Rin(3), Clock, R3); tri0: trin PORT MAP (R0, Rout(0), BusWires); tri1: trin PORT MAP (R1, Rout(1), BusWires); tri2: trin PORT MAP (R2, Rout(2), BusWires); tri3: trin PORT MAP (R3, Rout(3), BusWires); regA: regn PORT MAP (BusWires, Ain, Clock, A); alu: WITH AddSub SELECT Sum <= A+BusWires WHEN '0', A-BusWires WHEN OTHERS; regG: regn PORT MAP (Sum, Gin, Clock, G); triG: trin PORT MAP (G, Gout, BusWires); END Behavior;
Componentes LIBRARY ieee; USE ieee.std_logic_1164.all;
COMPONENT shiftr--registro de corrimiento de izquiera a derecha con reset asincrono GENERIC(K:INTEGER:=4); PORT(Resetn,Clock,w :IN STD_LOGIC; Q : BUFFER STD_LOGIC_VECTOR(1 TO K)); END component; COMPONENT trin--buffers triestado GENERIC(N:INTEGER:=8); PORT(X :IN STD_LOGIC_VECTOR(N-1 DOWNTO 0); E :IN STD_LOGIC; F :OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0)); END COMPONENT; END components;
