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Assignment 1

This document contains an assignment for a Circuit Analysis II course. It includes 6 questions related to analyzing circuits containing resistors, inductors, and capacitors. The questions involve deriving expressions for voltages and currents, determining initial and final values, calculating energy stored in capacitors, and designing parallel RLC circuits with specific oscillating voltage behaviors.

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UsamaQayyum
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60 views2 pages

Assignment 1

This document contains an assignment for a Circuit Analysis II course. It includes 6 questions related to analyzing circuits containing resistors, inductors, and capacitors. The questions involve deriving expressions for voltages and currents, determining initial and final values, calculating energy stored in capacitors, and designing parallel RLC circuits with specific oscillating voltage behaviors.

Uploaded by

UsamaQayyum
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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EE-3263 CIRCUIT ANALYSIS II

Assignment No 1
Due Date: 22-10-2014
Q-1 Derive an expression for v(t) valid for time t > 0.
a) Calculate the maximum inductor current and determine the time for which it occurs
b) Determine the rise time and settling time. How would the resistor effect the rise time and
settling time?

Q-2 Determine i
C
(0
-
), i
L
(0
-
), i
R
(0
-
), v
C
(0
-
), i
C
(0
+
), i
L
(0
+
), i
R
(0
+
), v
C
(0
+
)

Q-3 Resistor R
1
is 0.725 and resistor R
2
is 1.268.
a) Obtain and expression for energy stored in the capacitor valid for time t > 0
b) Determine the settling time for current i
A
in the circuit and plot the response


Q-4 Derive and expression for R in terms of L and C for a parallel RLC circuit to ensure that the
response is under-damped.
a) For C = 1nF and L = 10mH select R such that the response is just barely under-damped.
b) If damping ratio is increased does the circuit become more or less under-damped? Explain
why.

Q-5 Determine the first time t > 0 when v(t) = 0 also calculate the settling time.

Q-6 Design a parallel RLC circuit which provide a capacitor voltage that oscillates with a frequency
of 100 rad/s with a maximum value of 10V occurring at t=0s. The second and third maxima should
both be in excess of 6V.

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