HowdoesScanWork?

PreparedbyMahmutYilmaz
ScanChainOperationforStuckatTest

DesignUnderTest(DUT)
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Hereisanexampledesignundertest(DUT).Ihaveshownasinglescanchain(inredcolor)inthecircuit,withScanInandScanOutports.
AssumethatallscanflipflopsarecontrolledbytheScanEnablesignal.

1

HowdoesScanWork? PreparedbyMahmutYilmaz
DesignUnderTest(DUT)
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ScanOut
ScanIn
100101011

Thefirstthingweshoulddoistoputthescanflipflopsintoscanmode.WedothisbyusingtheScanEnablesignal.Inthiscase,forcingScan
Enableto1enablesthescanmode.
Notethatinitiallyallthescanflopsatunknownstate(X).Forindustrialcircuits,therearearchitecturalwaystoinitializeallflipflopstoknown
statesifneeded.However,forthisparticularcase,assumethatallscanflopswereinitiallyatunknownstateX.
Wewanttoscaninthefollowingvector:100101011

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HowdoesScanWork? PreparedbyMahmutYilmaz
DesignUnderTest(DUT)
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ScanIn
100101

Andwestartscanninginthetestvectorwewanttoapply.Inthefigureabove,youseethatthefirst3bitsarescannedin.Weshiftinasinglebit
ateachclockcycle.Usually,thescanshiftfrequencyisveryslow,muchlowerthanthefunctionalfrequencyofthecircuit.Thisfrequencyis
currentlyabout100MHzformostASICcircuits.AMDuses400MHzshiftfrequency,whichisaprettyhighvalueforthatpurpose.Ofcourse,the
higherthetestfrequency,theshorterthetesttime.

3

HowdoesScanWork? PreparedbyMahmutYilmaz
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ScanEnable=0
ScanOut

Atthispoint,wehaveshiftedinthecompletetestvector'100101011'.Wearedonewithshiftingin.WewilldisablescanmodebyforcingScan
Enableto0.
Notethattheshiftedintestvectoriscurrentlyappliedtothecombinationallogicpiecesthataredrivenbyscanflipflops.Itmeansthat2nd,
3rd,and4thcombinationallogicblocksarealreadyforcedtestinputs.

4

HowdoesScanWork? PreparedbyMahmutYilmaz
DesignUnderTest(DUT)
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Thenextstepistoforceprimaryinput(PI)valuesandmeasuretheprimaryoutput(PO)values:force_PIandmeasure_PO.
Notethatfromthepreviousstep,theshiftedintestvectorwasalreadyappliedtothecombinationallogicpiecesthataredrivenbyscanflip
flops.Itmeansthat2nd,3rd,and4thcombinationallogicblockswerealreadyforcedtestinputs.Now,thesecombinationallogicblockshave
generatedtheiroutputs.
SinceweforcedvaluestoPI,the1stcombinationalblockalsohasitsoutputsready.Furthermore,theoutputsofthe4thcombinationalblockcan
nowbeobservedfromPOs.Wewillgettheoutputvaluesofcombinationalblock4bymeasuringPOs.
Fortherestofthecombinationalblocks(1,2,and3),weneedtopushtheoutputvaluesintoscanflipflopsandthenshiftthesevaluesout.

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HowdoesScanWork? PreparedbyMahmutYilmaz
DesignUnderTest(DUT)
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ScanEnable=0
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Inordertopushtheoutputvaluesofcombinationalblocks1,2,and3intoscanflipflops,wehavetotogglethesystemclock.Oncewetogglethe
systemclock,allDflipflops(scanflipflops)willcapturethevaluesattheirDinput.
Inthefigureabove,thecaptureeventisshown.

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HowdoesScanWork? PreparedbyMahmutYilmaz
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111100111
ScanEnable=1
ScanOut

Now,wearereadytoshiftoutthecapturedcombinationallogicresponses.However,whiledoingthat,wewillalsoshiftinthenexttestvector.
Thenexttestvectoris'111100111'.
NotethatwehavesetScanEnablesignalbackto1toenableshifting.

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HowdoesScanWork? PreparedbyMahmutYilmaz
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0111
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11110
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Hereisasnapshotoftheshiftoperation.Asyoucansee,wehaveshiftedout4bitsoftheprevioustestresponse,andatthesametimeshifted
in4bitsofthenewtestvectorinput.Thenewtestvectorbitsareshowninboldredinthefigureabove.

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HowdoesScanWork? PreparedbyMahmutYilmaz
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011000111
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ScanEnable=1
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Atthispoint,wehavecompletelyscannedout(shiftedout)thetestresponsefortheprevioustestvector,andalsoscannedin(shiftedin)the
newtestvectorinput.
Theprocesscontinuesinthiswayuntilallthetestvectorsareapplied.
Note:Onpage5,Imentionedforce_PIandmeasure_PO.Actually,forindustrialcircuits,force_PIandmeasure_POisnotdone.Thisisbecause
primaryinputsandoutputsareconnectedtoveryslowpads,andthesepadsarenottestedbystructuraltest.Youmayrealizethatinthiscase
the 1st and 4th combinational blocks cannot be tested: 1st block cannot be tested because we cannot apply inputs to it (force_PI). 4th block
cannot be tested because we cannot check its output (measure_PO). This is usually not a problem because the circuits are surrounded by
wrapperscanflipflops.Thismeansthatthereisactuallynologicbeforethefirstlevelofscanflipflopsorafterthelastlevelofscanflipflops.
So,thecompleteDUTiscoveredbyscanflipflops.
9

HowdoesScanWork? PreparedbyMahmutYilmaz
ScanChainOperationforDelayTest
Scanoperationfordelaytestisverysimilartostuckattest.Themaindifferenceisthatdelaytestneedstwoinputsinsteadofone.Thefirstinput
isalwaysthescannedinvector.Thesecondinputcanbegeneratedintwodifferentways.Eachwayhasitsownname:(1)LaunchonCapture
(LOC)orbroadsidedelaytest,(2)Launchonshift(LOS)orskewedloaddelaytest.NowIwillshowhoweachofthesemethodsworks...
(1)LaunchonCapture(Broadside)
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Thisisthesamefigurethatisshownonpage5.Assumethatalltheprocessuntilthispointisthesameasstuckattest.Youscannedinthetest
vector, forced the PIs, and they created some output responses for combinational blocks. This is step 1. You have already applied your first
vectorforthedelaytest.Guesswhatisthesecondvector?Thesecondvectorwilltheoutputresponsesofthecombinationalblocks.Eachblock
willgeneratethe2ndtestvectorforthenextstage.Sincethereisnostagebeforethe1stone,youneedapplyforce_PIonemoretime.
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HowdoesScanWork? PreparedbyMahmutYilmaz
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DesignUnderTest(DUT)
ScanEnable=0
ScanOut

Of course, in order to push the output responses ofcombinational blocks into scan flipflops, we need to toggle system clock. Once we toggle
thesystemclock(andapplythesecondPIforce),wewillgeneratethesecondtestvectorforthedelaytest,andeachcombinationalcircuitinput
will see an input state transition. The transition on scan flipflop outputs (which are inputs to the next stage combinational block) will be as
follows(startingfromtheclosesttoscaninflop):100101110>010010111
Thesecondinputvectorwillgenerateoutputresponsesjustlikethefirstone.And,youneedtocapturetheseresponsesjustlikewedidbefore,
by toggling the system clock. However, now there is a difference: You have to toggle the system clock at the real operating frequency: This
means that the period between the first clock toggle and second clock toggle should be equal to functional clock period. In this way, you will
capturethedelaytestresponsesatthefunctionalfrequency.

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HowdoesScanWork? PreparedbyMahmutYilmaz
HereisatimingdiagramoftheLOCprocess(source:MentorGraphicsScanandATPGProcessGuide,August2006):

Asyoucanseeabove,weshiftthe testvectorusingaslowclockfrequency.Then,wesetscanenableto0anddisablescanmode.Inthenext
step, we toggle the clock first time to launch a transition in combinational blocks. After that, we toggle the clock again (at the functional
frequency)tocapturethefinalresponsesofthecombinationalblocks.Thelaunch&captureeventshappenatfunctionalfrequency.Finally,we
shiftedoutthecapturedresponsesusingtheslowclockfrequency.

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HowdoesScanWork? PreparedbyMahmutYilmaz
(2)LaunchonShift(SkewedLoad)
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Thisisthesamefigurethatisshownonpage5and10.So,westartasusual:Assumethatalltheprocessuntilthispointisthesameasstuckat
test. Youscannedin thetestvector,forced thePIs, andthey createdsomeoutputresponsesforcombinationalblocks.ForLOS, wedon't care
abouttheseinitialoutputresponses.Thisisstep1.Youhavealreadyappliedyourfirstvectorforthedelaytest.Sincethereisnostagebefore
the1stone,youneedapplyforce_PIonemoretime.NotethatScanEnablesignalisstillatactivevalue1.Thisisbecausewehavenotyetdone
withshifting.Weneedtoshiftonemoretimetocreatethesecondtestvectorforthedelaytest.

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ScanEnable=1
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Notethatasmentionedinthepreviouspage,thefirstvectorofthedelaytestis(startingfromtheclosesttoscaninflop):100101110
Thesecondtestvectorisgeneratedbyshiftingonemoretime,andinsertingonemorebitfromScanIn,2ndvectoris:010010101
Justafteryoushiftthelastbit(andlaunchedatransitionbyapplyingthesecondvector),youhavetoforceScanEnableto0,andalsotogglethe
systemclockatthefunctionalfrequency.Thelasttoggleofthesystemclockwillcapturethedelaytestresponses.Finally,youwillscanoutthe
responsesasusual.

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HowdoesScanWork? PreparedbyMahmutYilmaz
15

YoucanseethatweneedtohaveaveryfastScanEnablesignalinordertouseLOS.ScanEnableshouldbeabletoswitchfrom1to0withina
veryshorttime.ThisisusuallyadifficultprocessbecauseScanEnableisnotdesignedtooperateathighfrequencies.Duetothisreason,many
industrialdesignsuseLOCinsteadofLOS.(TherearesomedesignsthatuseLOS.ThereareworkaroundstofastScanEnablesignalrequirement,
butIwillnotgointodetailsfornow.)
Asyoucanseeabove,weshiftthetestvectorusingaslowclockfrequencyuntilthelastbit.ThelastshiftedbitcreatestheLaunchevent.Then,
before we toggle the system clock to capture responses, we set scan enable to 0 and disable scan mode. This has to happen very fast since
Launch & Capture event happen at high frequency. In the next step, we toggle the clock again to capture the final responses of the
combinationalblocks.Finally,weshiftedoutthecapturedresponsesusingtheslowclockfrequency.
HereisatimingdiagramoftheLOSprocess(source:MentorGraphicsScanandATPGProcessGuide,August2006):