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An Optimized Algorithm For Integer Division: Abstract

This document proposes an optimized algorithm for integer division that is more efficient than existing division algorithms. It introduces a sequential radix-2 integer division algorithm that reduces area, power, and delay compared to combinational radix-2 approaches. The algorithm is implemented in Verilog RTL, simulated, synthesized, and tested on an FPGA to demonstrate its improvements over prior integer division methods.

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24 views2 pages

An Optimized Algorithm For Integer Division: Abstract

This document proposes an optimized algorithm for integer division that is more efficient than existing division algorithms. It introduces a sequential radix-2 integer division algorithm that reduces area, power, and delay compared to combinational radix-2 approaches. The algorithm is implemented in Verilog RTL, simulated, synthesized, and tested on an FPGA to demonstrate its improvements over prior integer division methods.

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lkprasad
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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An Optimized Algorithm for Integer Division

ABSTRACT: 100PE100
In modern microprocessors which has to take many clock cycles to perform
the arithmetic and logical operations in digital system design. The arithmetic block
consists of number of subunits such as integer division, subtraction, multiplication
and division etc., among all these units integer division is a difficult job. In existing
system they designed combinational radix -2 integer division algorithm which
occupies more amount of area, power and delays are effected in digital system
designs. So, here we introduced a sequential radix-2 integer division algorithm
which reduces the area, power and delay and also it reduces the number of clock
cycles when compared to the existing system. Hence our proposed method can
eliminate the problems in existing systems.
The whole project work is implemented in synthesized Verilog RTL and it is
simulated and synthesized in Xilinx hardware compiler. The synthesized RTL
netlist is imported and implemented in FPGA Spartan 3E kit.
Index terms: Integer division, radix-2, restoring and non restoring algorithm.

Guided by Presented by
Dr. A. R. Reddy B. Rajeswar reddy
Prof& HOD of ECE 13695D8611, MNE
RBAWDAF

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