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Contents:: Instruction and Programming of TMS320C67XX. Interrupts of TMS320C67XX Processor

This document discusses instructions for the TMS320C67xx processor. It describes the ABSDP instruction which takes the absolute value of a double-precision floating point operand and places it in the destination register. It also describes the LDW instruction which loads a double word from memory to a pair of general purpose registers, using a base address and optional offset. The document covers additional instructions for the C67x processor.

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Paresh Sawant
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329 views

Contents:: Instruction and Programming of TMS320C67XX. Interrupts of TMS320C67XX Processor

This document discusses instructions for the TMS320C67xx processor. It describes the ABSDP instruction which takes the absolute value of a double-precision floating point operand and places it in the destination register. It also describes the LDW instruction which loads a double word from memory to a pair of general purpose registers, using a base address and optional offset. The document covers additional instructions for the C67x processor.

Uploaded by

Paresh Sawant
Copyright
© © All Rights Reserved
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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1 P.D.

Sawaant
Contents:

Instruction and Programming of TMS320C67XX.
Interrupts of TMS320C67XX processor.
P.D. Sawaant 2
Instruction of TMS320C67xx Processor.
Instructions common to C62x and C67xx
P.D. Sawaant 3
Instruction of TMS320C67xx Processor.
Extra Instructions for the C67x and functional unit maping
P.D. Sawaant 4
Instruction of TMS320C67xx Processor.
Instructions for the C67x
ABSDP : Double-Precision Floating-Point Absolute Value.
Syntax : ABSDP (.unit) src2, dst
.unit = .S1 or .S2
Description: The absolute value of src2 is placed in dst. The 64-bit
double-precision operand is read in one cycle by using the src2 port for
the 32 MSBs and the src1 port for the 32 LSBs.
Execution : if (cond) abs(src2) dst
else nop
The absolute value of src2 is determined as follows:
1) If src2 0, then src2 dst
2) If src2 < 0, then src2 dst
P.D. Sawaant 5
Instruction of TMS320C67xx Processor.
Instructions for the C67x
P.D. Sawaant 6
Instruction of TMS320C67xx Processor.
Instructions for the C67x
P.D. Sawaant 7
Instruction of TMS320C67xx Processor.
Instructions for the C67x
P.D. Sawaant 8
Instruction of TMS320C67xx Processor.
Instructions for the C67x
P.D. Sawaant 9
Instruction of TMS320C67xx Processor.
Instructions for the C67x
P.D. Sawaant 10
Instruction of TMS320C67xx Processor.
P.D. Sawaant 11
Instruction of TMS320C67xx Processor.
P.D. Sawaant 12
Instruction of TMS320C67xx Processor.
Description: This instruction loads a double word to a pair of
general-purpose registers (dst).
The memory address is formed from a base address register (baseR)
and an optional offset that is either a register (offsetR) or a 5-bit
unsigned constant (ucst5).
P.D. Sawaant 13
Instruction of TMS320C67xx Processor.
P.D. Sawaant 14
Instruction of TMS320C67xx Processor.
P.D. Sawaant 15
Instruction of TMS320C67xx Processor.

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