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Interview Questions: Difference Between Latch and Flip With Waveforms

This document contains 30 interview questions related to ASIC design, Verilog, timing analysis, functional verification, and testbenches. The questions cover topics such as abstraction levels in ASIC flow, setup and hold times, metastability, logic gate implementation, blocking vs non-blocking statements, timing delays, latches vs flip-flops, maximum operating frequency calculation, clock generation code, always block execution order, divide by circuits, finite state machine design, FIFO depth calculation, timing analysis challenges, functional vs code coverage, inferred latches, for loop execution count, functional verification, polymorphism, abstract classes, coverage types, clocking blocks, avoiding race conditions between testbench and DUT, event queues, deep copy

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Charan J Gowda
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52 views2 pages

Interview Questions: Difference Between Latch and Flip With Waveforms

This document contains 30 interview questions related to ASIC design, Verilog, timing analysis, functional verification, and testbenches. The questions cover topics such as abstraction levels in ASIC flow, setup and hold times, metastability, logic gate implementation, blocking vs non-blocking statements, timing delays, latches vs flip-flops, maximum operating frequency calculation, clock generation code, always block execution order, divide by circuits, finite state machine design, FIFO depth calculation, timing analysis challenges, functional vs code coverage, inferred latches, for loop execution count, functional verification, polymorphism, abstract classes, coverage types, clocking blocks, avoiding race conditions between testbench and DUT, event queues, deep copy

Uploaded by

Charan J Gowda
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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INTERVIEW QUESTIONS

1. ASIC Flow with tools used at diferent abstraction levels


2. What is setup and hold time. How to overcome it?
3. What is metastability? How to overcome it?
4. Implementation of ates ! and"or"nand# usin mu$
5. %$plain bloc&in and non'bloc&in statements
6. %$plain intra statement and inter statement delays with e$ample
7. (iference between latch and )ip with waveforms
8. Calculate the ma$ operatin fre*uency
Setup time+,ns" hold time+-ns"propaation delay+-.ns
9. Write a code to enerate a cloc& of /..0H1
10. In the followin code what value of 2a3 is displayed
always@(clc!"
#$%&'
a(0)
a*(1)
+,&s-lay(a")
$',
11. (ivide by - circuit
12. (ivide by 4 circuit with ,.5 duty cycle
13. Write a FS0 to detect a se*uence //./ with overlap
14. FIF6 depth calculation
15. Why timin analysis of latch is di7cult
16. What is the diference between the two codes below
If !foo# c+foo?a8b9
C+a9
%lse
C+b9
17. If code coverae /..5 and functional coverae is less than /..5 .
18. What is meant by inferrin latches. How to avoid it?
19. How many times this loop will get executed?
reg i[3:0];
for (i=0;i=!"; i=i#!$
%egin
&&&&&&&
end
20. What is functional veri:cation.
21. What is polymorphism
22. What is abstract class
23. %$plain diferent types of coveraes
24. what is the need of cloc&in bloc& in system verilo
25. What are the ways to avoid race around condition between
testbench and (;<
26. %$plain event *ueue system verilo
27. %$plain deep copy
28. What is :nal bloc&
29. Write <estbench architecture in system verilo
30. What is the use of e$tern

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