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FPGA Implementation of Convolution in Verilog

This document discusses implementing convolution in Verilog on an FPGA. Convolution is an important concept in digital signal processing that combines two signals to form a third. Implementing convolution efficiently can reduce power, hardware resources, and area compared to DSP systems. FPGAs are well-suited for this as they allow implementing complex logic circuits and interfacing with other systems. The document outlines the basic building blocks used and approaches for coding the convolution in Verilog or by generating Verilog code from Matlab.

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DevanshGoenka
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474 views

FPGA Implementation of Convolution in Verilog

This document discusses implementing convolution in Verilog on an FPGA. Convolution is an important concept in digital signal processing that combines two signals to form a third. Implementing convolution efficiently can reduce power, hardware resources, and area compared to DSP systems. FPGAs are well-suited for this as they allow implementing complex logic circuits and interfacing with other systems. The document outlines the basic building blocks used and approaches for coding the convolution in Verilog or by generating Verilog code from Matlab.

Uploaded by

DevanshGoenka
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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IMPLEMENTATION OF

CONVOLUTION IN VERILOG
REVIEW-I
BY: Devansh Goenka(11BEC1099)
REGISTERED UNDER

Prof. Shaktivel
(SENSE)
VLSI System Design(ECE301)
Abstract
The Purpose of this project is to perform FPGA
implementation of convolution in Verilog
efficiently which reduces power hardware
resources, and area significantly unlike the
performance in DSP Systems.
What is a convolution??
Convolution is a
mathematical way of
combing to signal to
form a third signal.

It is important concept
in DSP(DIGITAL SIGNAL
PROCESSING) because
convolving to sequence
in time domain is
equivalent to
multiplying a sequence
in frequency domain.
Field Programmable Gate Array
A Field Programmable Gate Array (FPGA) is a programmable logic
device that supports the implementation of large logic circuit.

FPGA contains three main type of resources
I. Logic Blocks.
II. I/O Blocks for connecting the pins of the package.
III. Interconnection wires and switches.

Why FPGA??

The main problem in implementing and computing
convolution is speed, area and power which affect any
DSP system. Speeding up convolution using a Hardware
Description Language for design entry not only
increases (improves) the level of abstraction, but also
opens new possibilities for using programmable
devices.




Today, most DSP Systems suffer mainly from:

1. Limitations in available address space.
2. The ability to interface with surrounding systems.
3. Speed, Area and Power.

The use of high speed FPGAs, together with DSPs, can
often increase the system bandwidth, by providing
additional functionality to the general purpose DSPs

Convolution of two discrete sequence
Figure shows the convolution flow of two 16-bit numbers, in 4-bit segments. The letters A, B, C,
D, E, F, G, and H each represent 4 bits of the 16 bits number.
Basic Building Blocks Used in
the Design
Sub Blocks used inside the design
Coding for the convolution
One approach is Matlab. It is used to automatically
generate Verilog code for the hardware implementation
of convolution algorithms.

Or

Use the Verilog code itself.

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