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Xilinx Ise 9.1I: Objective

This document describes how to simulate a half adder using Xilinx ISE 9.1i software. It begins with an overview of what a half adder is - a logic circuit that performs addition on two bits of binary numbers. It then outlines the 15 steps to create a new project in ISE, write the VHDL code for a half adder, synthesize and view the resulting schematic. The conclusion states that the half adder simulation was successfully completed.

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tarun06
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124 views11 pages

Xilinx Ise 9.1I: Objective

This document describes how to simulate a half adder using Xilinx ISE 9.1i software. It begins with an overview of what a half adder is - a logic circuit that performs addition on two bits of binary numbers. It then outlines the 15 steps to create a new project in ISE, write the VHDL code for a half adder, synthesize and view the resulting schematic. The conclusion states that the half adder simulation was successfully completed.

Uploaded by

tarun06
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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OBJECTIVE:-

Simulation of fundamental unit Half adder



Software required:-
XILINX ISE 9.1i

Theory:-

Halfadder:-
A device that can add two binary digits together. We can quickly calculate what the answers should be:
0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 10
2

So we will need two inputs (a and b) and two outputs. The low order output will be called because it
represents the sum, and the high order output will be called C
out
because it represents the carry out.
The truth table is

Simplifying Boolean equations or making some Karnaugh map will produce the same circuit shown below,
but start by looking at the results. The column is our familiar XOR gate, while the C
out
column is the AND
gate. This device is called a half-adder for reasons that will make sense in the next section.



Procedure:-
Step1:
To simulate the functional working of half adder we need XILINX 9.1i to run in Admin mode as shown
below.

Step2:
Go to file menu and chose new project.

Step3:
Type the project name and then choose the top level source type as HDL.

Stpe4:
Set the parameter in the window as
Family- Spantan3
Device-XC3S200
Package-FT256
Speed- 4
Preferred Language-VHDL
And press next

Step5:
Choose the new source and press next and whenever the new window open, Put the same file name and
choose VHDL module


Step6:
In the next window input two port names as input1 and input2 and direction as in. Then input two port
names as sum and carry and set direction as out.

Step7: And press next.

Step8: Press next

Step9: Press next

Step10: Press next

Step11:Press finish

Step12: Write the HDL code for half adder followed by begin.

Step13:
Double click on the Synthesize.xst and go to check syntax and if error not found the following screen
appear.


Step14:
Then click on the view RTL schme

Step15:Then following output screen output screen appear.


.

Conclusion:-

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