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ICs' Pin Configuration

The document describes the pin configurations of several common integrated circuits in the 7400 series of TTL logic chips. It provides details on the pin assignments for common logic gates like NAND, NOR, AND and XOR gates, as well as more complex chips like 4-bit adders and multiplexers. The pin configurations specify the functions of each pin, such as inputs, outputs and power supply connections for each IC.

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Ratinan Lee
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429 views2 pages

ICs' Pin Configuration

The document describes the pin configurations of several common integrated circuits in the 7400 series of TTL logic chips. It provides details on the pin assignments for common logic gates like NAND, NOR, AND and XOR gates, as well as more complex chips like 4-bit adders and multiplexers. The pin configurations specify the functions of each pin, such as inputs, outputs and power supply connections for each IC.

Uploaded by

Ratinan Lee
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Pin Configuration of Some ICs in 74-Series

SSI
Quad 2-input NAND gate (Y = A nand B)
14: X 13: IN 12: IN 11: OUT 10: IN 9: IN 8: OUT
7400 Vcc A4 B4 Y4 A3 B3 Y3
1: IN 2: IN 3: OUT 4: IN 5: IN 6: OUT 7: X
A1 B1 Y1 A2 B2 Y2 GND
Quad 2-input NOR gate (Y = A nor B)
14: X 13: OUT 12: IN 11: IN 10: OUT 9: IN 8: IN
7402 Vcc Y4 A4 B4 Y3 A3 B3
1: OUT 2: IN 3: IN 4: OUT 5: IN 6: IN 7: X
Y1 A1 B1 Y2 A2 B2 GND
Quad 2-input NAND gate with Open Collector Outputs (Y = A nand B)
14: X 13: IN 12: IN 11: OUT 10: IN 9: IN 8: OUT
7403 Vcc A4 B4 Y4 A3 B3 Y3
1: IN 2: IN 3: OUT 4: IN 5: IN 6: OUT 7: X
A1 B1 Y1 A2 B2 Y2 GND
Hex Inverter
14: X 13: IN 12: OUT 11: IN 10: OUT 9: IN 8: OUT
7404 Vcc A6 A6’ A5 A5’ A4 A4’
1: IN 2: OUT 3: IN 4: OUT 5: IN 6: OUT 7: X
A1 A1’ A2 A2’ A3 A3’ GND
Quad 2-input AND gate (Y = A and B)
14: X 13: IN 12: IN 11: OUT 10: IN 9: IN 8: OUT
7408 Vcc A4 B4 Y4 A3 B3 Y3
1: IN 2: IN 3: OUT 4: IN 5: IN 6: OUT 7: X
A1 B1 Y1 A2 B2 Y2 GND
Quad 2-input NAND gate with Open Collector Outputs (Y = A and B)
14: X 13: IN 12: IN 11: OUT 10: IN 9: IN 8: OUT
7409 Vcc A4 B4 Y4 A3 B3 Y3
1: IN 2: IN 3: OUT 4: IN 5: IN 6: OUT 7: X
A1 B1 Y1 A2 B2 Y2 GND
Quad 2-input OR gate (Y = A or B)
14: X 13: IN 12: IN 11: OUT 10: IN 9: IN 8: OUT
7432 Vcc A4 B4 Y4 A3 B3 Y3
1: IN 2: IN 3: OUT 4: IN 5: IN 6: OUT 7: X
A1 B1 Y1 A2 B2 Y2 GND
Dual 2-wide 2-input AND-OR-INVERT gate (Y = (A1·A2+B1·B2)’)
14: X 13: IN2 12: - 11: - 10: IN2 9: IN2 8: OUT2
7451 Vcc A2 B1 B2 Y
1: IN2 2: IN1 3: IN1 4: IN1 5: IN1 6: OUT1 7: X
A1 A1 A2 B1 B2 Y GND
Quad 2-input XOR gate (Y = A xor B)
14: X 13: IN 12: IN 11: OUT 10: IN 9: IN 8: OUT
7486 Vcc A4 B4 Y4 A3 B3 Y3
1: IN 2: IN 3: OUT 4: IN 5: IN 6: OUT 7: X
A1 B1 Y1 A2 B2 Y2 GND

Digital Circuits > ICs | LeckerStudy | 1


MSI
4-bit Binary Full Adder (S = X+Y)
16: IN 15: OUT 14: OUT 13: IN 12: X 11: IN 10: IN 9: OUT
7483 X4 S4 C4 C0 GND X1 Y1 S1
1: IN 2: OUT 3: IN 4:IN 5: X 6: OUT 7: IN 8: IN
Y4 S3 Y3 X3 Vcc S2 X2 Y2
Quad 2-lind to 1-line Data Selector/Multiplexer (MUX)
Active LOW Enable, Y = A <-> S = 0, Y = B <-> S = 1
7415 16: X 15: IN 14: IN 13: IN 12: OUT 11: IN 10: IN 9: OUT
7 Vcc ENABLE A3 B3 Y3 A4 B4 Y4
1: IN 2: IN 3: IN 4: OUT 5: IN 6: IN 7: OUT 8: X
SELECT A1 B1 Y1 A2 B2 Y2 GND

Digital Circuits > ICs | LeckerStudy | 2

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