Sri Venkateswara College of Engineering & Technology

R.V.S Nagar, Chittoor

M.Tech. I SEMESTER (DECS)
DIIT!" S#STEM DESIN "!$
"ist of E%&eri'ents

1. Simulation and Verification of Logic Gates.
2. Design and Simulation of
(a) Half adder (b) Full adder (c) Serial Binary adder
(d) arry Loo! "#ead adder (e) $i%%le arry adder
&. Simulation and Verification of
(a) Decoder (b) 'u( (c) )ncoder
* 'odeling of Fli%+Flo%s
(a) S$ Fli%+Flo%s (b) D Fli%+Flo%s
(c) ,- Fli%+Flo%s (d) . Fli%+Flo%s
/. Design and Simulation of ounters
(a) $ing ounters (b) ,o#nson ounters
(c) 0%+Do1n ounters (d) $i%%le ounters ("sync#ronous)
2. Design of a 3+ bit $egister
(a) Serial+in Serial+out (b) Serial in 4arallel out
(c) 4arallel in Serial out (d) 4arallel in 4arallel out
5. Design of Se6uence detector.
7. *+Bit 'ulti%lier ("rray)
8. Design of "L0.
19. $"' ($ead and :rite ;%erations)
11. Stac! and <ueue =m%lementation.
"a()In)charge *+D, ECE
"+IC !TES
E%. No , -.
!IM ,)
.o 1rite a VHDL ode for reali>ing Gates
"3D? ;$? 3;.? 3"3D? 3;$? @;$? @3;$
"nd Aerify t#e results.
!ND !TE
/R+R!M,)
library =)))B
use =))).S.DCL;G=C112*."LLB
use =))).S.DCL;G=C"$=.H."LLB
use =))).S.DCL;G=C03S=G3)D."LLB
entity and2 is
4ort ( a D in S.DCL;G=B
b D in S.DCL;G=B
c D out S.DCL;G=)B
end and2B
arc#itecture dataCflo1 of and2 is
begin
cEFa and bB
end dataCflo1B
arc#itecture be#aAioral of and2 is
begin
%rocess(a?b)
begin
if aFG1G and bFG1G
t#en cEFG1GB
else cEFG9GB
end ifB
end %rocessB
end be#aAioralB
arc#itecture structural of and2 is
com%onent and( is
4ort ( ( D in S.DCL;G=B
y D in S.DCL;G=B
> D out S.DCL;G=)B
end com%onentB
begin
"1Dand( %ort ma%(a?b?c)B
end structuralB
library =)))B
use =))).S.DCL;G=C112*."LLB
use =))).S.DCL;G=C"$=.H."LLB
use =))).S.DCL;G=C03S=G3)D."LLB
entity and( is
4ort ( ( D in S.DCL;G=B
y D in S.DCL;G=B
> D out S.DCL;G=)B
end and(B
arc#itecture and( of and( is
begin
>EF( and yB
end and(B
+R !TE
/R+R!M,)
library =)))B
use =))).S.DCL;G=C112*."LLB
use =))).S.DCL;G=C"$=.H."LLB
use =))).S.DCL;G=C03S=G3)D."LLB
entity or2 is
4ort ( a D in S.DCL;G=B
b D in S.DCL;G=B
c D out S.DCL;G=)B
end or2B
arc#itecture dataCflo1 of or2 is
begin
cEFa or bB
end dataCflo1B
arc#itecture be#aAioral of or2 is
begin
%rocess(a?b)
begin
if aFG9G and bFG9G
t#en cEFG9GB
else cEFG1GB
end ifB
end %rocessB
end be#aAioralB
arc#itecture structural of or2 is
com%onent or( is
4ort ( ( D in S.DCL;G=B
y D in S.DCL;G=B
> D out S.DCL;G=)B
end com%onentB
begin
"1Dor( %ort ma%(a?b?c)B
end structuralB
library =)))B
use =))).S.DCL;G=C112*."LLB
use =))).S.DCL;G=C"$=.H."LLB
use =))).S.DCL;G=C03S=G3)D."LLB
entity or( is
4ort ( ( D in S.DCL;G=B
y D in S.DCL;G=B
> D out S.DCL;G=)B
end or(B
arc#itecture or( of or( is
begin
>EF( or yB
end or(B

N+T !TE
/R+R!M,)
library =)))B
use =))).S.DCL;G=C112*."LLB
use =))).S.DCL;G=C"$=.H."LLB
use =))).S.DCL;G=C03S=G3)D."LLB
entity not1 is 4ort ( a D in S.DCL;G=B
b D out S.DCL;G=)B
end not1B
arc#itecture dataCflo1 of not1 is
begin
bEFnot aB
end dataCflo1B
arc#itecture be#aAioral of not1 is
begin
%rocess(a)
begin
if aFG9G
t#en bEFG1GB
else bEFG9GB
end ifB
end %rocessB
end be#aAioralB
arc#itecture structural of not1 is
com%onent not( is
4ort ( ( D in S.DCL;G=B
y D out S.DCL;G=)B
end com%onentB
begin
"1Dnot( %ort ma%(a?b)B
end structuralB
library =)))B
use =))).S.DCL;G=C112*."LLB
use =))).S.DCL;G=C"$=.H."LLB
use =))).S.DCL;G=C03S=G3)D."LLB
entity not( is
4ort ( ( D in S.DCL;G=B
y D out S.DCL;G=)B
end not(B
arc#itecture not( of not( is
begin yEFnot (B
end not(B
N!ND !TE
/R+R!M,)
library =)))B
use =))).S.DCL;G=C112*."LLB
use =))).S.DCL;G=C"$=.H."LLB
use =))).S.DCL;G=C03S=G3)D."LLB
entity nand2 is
4ort ( a D in S.DCL;G=B
b D in S.DCL;G=B
c D out S.DCL;G=)B
end nand2B
arc#itecture dataCflo1 of nand2 is
begin
cEFa nand bB
end dataCflo1B
arc#itecture be#aAioral of nand2 is
begin
%rocess(a?b)
begin
if aFG1G and bFG1G
t#en cEFG9GB
else cEFG1GB
end ifB
end %rocessB
end be#aAioralB
arc#itecture structural of nand2 is
com%onent nand( is
4ort ( ( D in S.DCL;G=B
y D in S.DCL;G=B
> D out S.DCL;G=)B
end com%onentB
begin
"1Dnand( %ort ma%(a?b?c)B
end structuralB
library =)))B
use =))).S.DCL;G=C112*."LLB
use =))).S.DCL;G=C"$=.H."LLB
use =))).S.DCL;G=C03S=G3)D."LLB
entity nand( is
4ort ( ( D in S.DCL;G=B
y D in S.DCL;G=B
> D out S.DCL;G=)B
end nand(B
arc#itecture nand( of nand( is
begin
>EF( nand yB
end nand(B
N+R !TE
/R+R!M,)
library =)))B
use =))).S.DCL;G=C112*."LLB
use =))).S.DCL;G=C"$=.H."LLB
use =))).S.DCL;G=C03S=G3)D."LLB
entity nor2 is
4ort ( a D in S.DCL;G=B
b D in S.DCL;G=B
c D out S.DCL;G=)B
end nor2B
arc#itecture dataCflo1 of nor2 is
begin
cEFa nor bB
end dataCflo1B
arc#itecture be#aAioral of nor2 is
begin
%rocess(a?b)
begin
if aFG9G and bFG9G
t#en cEFG1GB
else cEFG9GB
end ifB
end %rocessB
end be#aAioralB
arc#itecture structural of nor2 is
com%onent nor( is
4ort ( ( D in S.DCL;G=B
y D in S.DCL;G=B
> D out S.DCL;G=)B
end com%onentB
begin
"1Dnor( %ort ma%(a?b?c)B
end structuralB
library =)))B
use =))).S.DCL;G=C112*."LLB
use =))).S.DCL;G=C"$=.H."LLB
use =))).S.DCL;G=C03S=G3)D."LLB
entity nor( is
4ort ( ( D in S.DCL;G=B
y D in S.DCL;G=B
> D out S.DCL;G=)B
end nor(B
arc#itecture nor( of nor( is
begin
>EF( nor yB
end nor(B
0+R !TE
/R+R!M,)
library =)))B
use =))).S.DCL;G=C112*."LLB
use =))).S.DCL;G=C"$=.H."LLB
use =))).S.DCL;G=C03S=G3)D."LLB
entity (or2 is
4ort ( a D in S.DCL;G=B
b D in S.DCL;G=B
c D out S.DCL;G=)B
end (or2B
arc#itecture dataCflo1 of (or2 is
begin
cEFa (or bB
end dataCflo1B
arc#itecture be#aAioral of (or2 is
begin
%rocess(a?b)
begin
if aFb
t#en cEFG9GB
else cEFG1GB
end ifB
end %rocessB
end be#aAioralB
arc#itecture structural of (or2 is
com%onent (or( is
4ort ( ( D in S.DCL;G=B
y D in S.DCL;G=B
> D out S.DCL;G=)B
end com%onentB
begin
"1D(or( %ort ma%(a?b?c)B
end structuralB
library =)))B
use =))).S.DCL;G=C112*."LLB
use =))).S.DCL;G=C"$=.H."LLB
use =))).S.DCL;G=C03S=G3)D."LLB
entity (or( is
4ort ( ( D in S.DCL;G=B
y D in S.DCL;G=B
> D out S.DCL;G=)B
end (or(B
arc#itecture (or( of (or( is
begin
>EF( (or yB
end (or(B
0N+R !TE
/R+R!M,)
library =)))B
use =))).S.DCL;G=C112*."LLB
use =))).S.DCL;G=C"$=.H."LLB
use =))).S.DCL;G=C03S=G3)D."LLB
entity (nor2 is
4ort ( a D in S.DCL;G=B
b D in S.DCL;G=B
c D out S.DCL;G=)B
end (nor2B
arc#itecture dataCflo1 of (nor2 is
begin
cEFa (nor bB
end dataCflo1B
arc#itecture be#aAioral of (nor2 is
begin
%rocess(a?b)
begin
if aFb
t#en cEFG1GB
else cEFG9GB
end ifB
end %rocessB
end be#aAioralB
arc#itecture structural of (nor2 is
com%onent (nor( is
4ort ( ( D in S.DCL;G=B
y D in S.DCL;G=B
> D out S.DCL;G=)B
end com%onentB
begin
"1D(nor( %ort ma%(a?b?c)B
end structuralB
library =)))B
use =))).S.DCL;G=C112*."LLB
use =))).S.DCL;G=C"$=.H."LLB
use =))).S.DCL;G=C03S=G3)D."LLB
entity (nor( is
4ort ( ( D in S.DCL;G=B
y D in S.DCL;G=B
> D out S.DCL;G=)B
end (nor(B
arc#itecture (nor( of (nor( is
begin
>EF( (nor yB
end (nor(B
M+DE"IN +1 !DDERS
E%. No , -2
!IM ,)
.o 1rite a VHDL ode for
Half adder
Full adder
ri%%le carry adder
carry loo! a#ead adder
serial adder
"nd Aerify t#e results.
*!"1 !DDER
/R+R!M,)
library =)))B
use =))).S.DCL;G=C112*."LLB
use =))).S.DCL;G=C"$=.H."LLB
use =))).S.DCL;G=C03S=G3)D."LLB
entity #a is
4ort ( a D in S.DCL;G=B
b D in S.DCL;G=B
sumD out S.DCL;G=B
carryD out S.DCL;G=)B
end #aB
arc#itecture dataCflo1 of #a is
begin
sumEFa (or bB
carryEF a and bB
end dataCflo1B
arc#itecture be#aAioral of #a is
begin
%rocess(a?b)
begin
if aFb
t#en sumEFG9GB
else sumEFG1GB
end ifB
if aFG1G and bFG1G
t#en carryEFG1GB
else carryEFG9GB
end ifB
end %rocessB
end be#aAioralB
arc#itecture structural of #a is
com%onent (or( is
4ort ( ( D in S.DCL;G=B
y D in S.DCL;G=B
> D out S.DCL;G=)B
end com%onentB
com%onent and( is
4ort ( ( D in S.DCL;G=B
y D in S.DCL;G=B
> D out S.DCL;G=)B
end com%onentB

begin
(1D(or( %ort ma%(a?b?sum)B
"1Dand( %ort ma%(a?b?carry)B
end structuralB
13"" !DDER
/R+R!M,)
library =)))B
use =))).stdClogicC112*.allB
entity adder is
%ort (a D in stdClogicB
b D in stdClogicB
cin D in stdClogicB
sum D out stdClogicB
cout D out stdClogic)B
end adderB
++ descri%tion of adder using concurrent signal assignments
arc#itecture rtl of adder is
begin
sum EF (a (or b) (or cinB
cout EF (a and b) or (cin and a) or (cin and b)B
end rtlB
++ descri%tion of adder using com%onent instantiation statements
use 1or!.gates.allB
arc#itecture structural of adder is
signal (or1Cout?
and1Cout?
and2Cout?
or1Cout D stdClogicB
begin
(or1D (org %ort ma%(
in1 FH a?
in2 FH b?
out1 FH (or1Cout)B
(or2D (org %ort ma%(
in1 FH (or1Cout?
in2 FH cin?
out1 FH sum)B
and1D andg %ort ma%(
in1 FH a?
in2 FH b?
out1 FH and1Cout)B
or1D org %ort ma%(
in1 FH a?
in2 FH b?
out1 FH or1Cout)B
and2D andg %ort ma%(
in1 FH cin?
in2 FH or1Cout?
out1 FH and2Cout)B
or2D org %ort ma%(
in1 FH and1Cout?
in2 FH and2Cout?
out1 FH cout)B
end structuralB
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++ 3+bit adder
++ .#e 1idt# of t#e adder is determined by generic 3
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library =)))B
use =))).stdClogicC112*.allB
entity adder3 is
generic(3 D integer DF 12)B
%ort (a D in stdClogicCAector(3 do1nto 1)B
b D in stdClogicCAector(3 do1nto 1)B
cin D in stdClogicB
sum D out stdClogicCAector(3 do1nto 1)B
cout D out stdClogic)B
end adder3B
++ structural im%lementation of t#e 3+bit adder
arc#itecture structural of adder3 is
com%onent adder
%ort (a D in stdClogicB
b D in stdClogicB
cin D in stdClogicB
sum D out stdClogicB
cout D out stdClogic)B
end com%onentB
signal carry D stdClogicCAector(9 to 3)B
begin
carry(9) EF cinB
cout EF carry(3)B
++ instantiate a single+bit adder 3 times
genD for = in 1 to 3 generate
addD adder %ort ma%(
a FH a(=)?
b FH b(=)?
cin FH carry(= + 1)?
sum FH sum(=)?
cout FH carry(=))B
end generateB
end structuralB
++ be#aAioral im%lementation of t#e 3+bit adder
arc#itecture be#aAioral of adder3 is
begin
%1D %rocess(a? b? cin)
Aariable Asum D stdClogicCAector(3 do1nto 1)B
Aariable carry D stdClogicB
begin
carry DF cinB
for i in 1 to 3 loo%
Asum(i) DF (a(i) (or b(i)) (or carryB
carry DF (a(i) and b(i)) or (carry and (a(i) or b(i)))B
end loo%B
sum EF AsumB
cout EF carryB
end %rocess %1B
end be#aAioralB
RI//"E C!RR# !DDER
/R+R!M,)
library =)))B
0se =))).S.DCL;G=C112*."llB
0se =))).S.DCL;G=C"$=.H."llB
0se =))).S.DCL;G=C03S=G3)D."llB
entity rea is
4ort (aD in stdClogic CAector (& do1nto 9)B
bD in stdClogic CAector (& do1nto 9)B
ciDin stdClogicB
sD out stdClogic CAector (& do1nto 9)B
coDin out stdClogic)B
end reaB
arc#itecture structural of rea is
signal cDstdC logic Aector(& do1nto 1)B
com%onent fa is
%ort (a?b?cinD in stdClogicB
s D out stdClogicB
coutD in out stdClogic)B
end com%onentB
begin
f1D fa %ort ma%( a(9)? b(9)? ci? s(9)?c(1))B
f2D fa %ort ma%(a(1)? b(1)? c(1)? s(1)?c(2))B
f&D fa %ort ma%(a(2)? b(2)? c(2)? s(2)?c(&))B
f*D fa %ort ma%(1)%(a(&)? b(&)? c(&)? s(&)?c(9))B
end structuralB
C!RR# "++4 !*E!D !DDER
/R+R!M,)
library =)))B
0se =))).S.DCL;G=C112*."llB
0se =))).S.DCL;G=C"$=.H."llB
0se =))).S.DCL;G=C03S=G3)D."llB
entity carryCloo!Ca#ead is
4ort (aD in stdClogic CAector(& do1nto 9)B
b D in stdClogic CAector(& do1nto 9)B
co D out stdClogicB
c D inout stdClogic CAector(* do1nto 9)B
s D out stdClogic CAector(& do1nto 9)B
end carryCloo!Ca#eadB
arc#itecture structural of carryCloo!Ca#ead is
signal %?gDstdC logic CAector(& do1nto 9)B
signal r D stdC logicC Aector(2 do1nto 9)B
signal i D integerB
begin
%rocessor(a?b?c?%?g?r)
begin
l1 D for i in 9 to & loo%
%(i)EFa(i) (or b(i)B
g(i)EFa(i) and b(i)B
c(9)EFI9IB
end loo% l1B
r(9)EF%(2)and g(1)B
r(1)EF%(2)and %(1)and g(9)B
r(2)EF%(2)and %(1)and %(9)and c(9)B
r(&)EF%(&)and g(2)B
r(*)EF%(&)and %(2)and g(1)B
r(/)EF%(&)and %(2)and %(1)and g(9)B
r(2)EF%(&)and %(2)and %(1)and %(9) and c(9)B
c(1)EFg(9)or ( %(9) and c(9))B
c(2)EFg(1)or ( %(1) and g(9)) or( %(1)and ( %(9) and c(9))B
c(&)EFg(2)or r(9) or r(1) or r(2)B
c(*)EFg(&)or r(&) or r(*) or r(/) or r(2)B
l2D for i in 9 to & loo%
s(i)EF%(i) (or c(i)B
end loo% l2B
c(9)EFc(*)B
end %rocessB
end Be#aAioralB
SERI!" !DDER
/R+R!M,)
library =)))B
0se =))).S.DCL;G=C112*."llB
0se =))).S.DCL;G=C"$=.H."llB
0se =))).S.DCL;G=C03S=G3)D."llB
entity serialCadder is
4ort ((D in stdClogic CAector(& do1nto 9)B
y D in stdClogic CAector(& do1nto 9)B
cl! D in stdClogicB
ceDin stdClogicB
cout D inout stdClogic
s D out stdClogic

end serialCadderB
arc#itecture structural of serialCadder is
signal cDstdC logicC Aector(* do1nto 9)B
signal i D integerB
begin
%rocessor(cl!?(?y)
begin
if (ceIeAent and ce FI1I)t#en
c(9)EFI9IB
sEFI9IB
iEFI9IB
end ifB
if (ceIeAent and cl! FI1I)t#en
sEF(((i)(or y(i) (or c(i)B
c(iJ1)EF(((i)and y(i))or (y(i)and c(i))or (c(i)and ((i))B
iEFiJ1B
end ifB
else
iEF9B
end ifB
coutEFc(*)B
end %rocessB
end Be#aAioralB
E0.No,) -5
5,6 DEC+DER

"='D .o 1rite and simulate a A#dl %rogram for a & to 7 decoder and Aerify t#e
results
/R+R!M,)
library ieeeB
use ieee.stdClogicC112*.allB
use ieee.stdClogicCarit#.allB
use ieee.stdClogicCunsigned.allB
entity dcCcounter is
%ort(cl!Din stdClogicB
6Dinout stdClogicCAector(& do1nto 9)DFK9999K)B
end dcCcounterB
arc#itecture be#aAe of dcCcounter is
begin
%rocess(cl!)
begin
if(cl!GeAent and cl!FG1G)t#en
if(6FK1991K)t#en
6EFK9999KB
else
6EF6J1B
end ifB
end ifB
end %rocessB
end be#aAeB
6%. M3"TI/"E0ER

"='D+ .o 1rite and simulate a'odelsim( VHDL) %rogram for 7(1 'ulti%le(er.
4$;G$"'D+
library ieeeB
use ieee.stdClogicC112*.allB
entity m( is
%ort(iDin stdClogicCAector(5 do1nto 9)B
sDin stdClogicCAector(2 do1nto 9)B
yDout stdClogic)B
end m(B
arc#itecture arc#i of m( is
begin
%rocess(i?s)
begin
if(sFK999K) t#en yEFi(9)B
elsif(sFK991K) t#en yEFi(1)B
elsif(sFK919K) t#en yEFi(2)B
elsif(sFK911K) t#en yEFi(&)B
elsif(sFK199K) t#en yEFi(*)B
elsif(sFK191K) t#en yEFi(/)B
elsif(sFK119K) t#en yEFi(2)B
elsif(sFK111K) t#en yEFi(5)B
end ifB
end %rocessB
end arc#iB
M+DE"IN +1 1"I/ + 1"+/S
E%. No , -7
!IM , )
.o 1rite a VHDL ode for
SR 1li&)1lo&
D 1li&)1lo&
84 1li&)1lo&
T 1li&)1lo&
"nd Aerify t#e results.
SR + 1"I/ + 1"+/
/R+R!M,)
library =)))B
0se =))).S.DCL;G=C112*."llB
0se =))).S.DCL;G=C"$=.H."llB
0se =))).S.DCL;G=C03S=G3)D."llB
entity srff is
4ort (s D in stdClogicB
r D in stdClogicB
cl! D in stdClogicB
6 D in out stdClogicB
6bar D in out stdClogic)B
end srffB
arc#itecture Be#aAioral of srff is
begin
4rocess (s?cl!?r)
begin
if (cl!IeAent and cl! FI1I)t#en
if(sFI9Iand rFI9I)t#en
6EF6B
6barEF6barB
elsif(sFI1Iand rFI9I)t#en
6EFI1IB
6barEFI9IB
elsif(sFI9Iand rFI1I)t#en
6EFI9IB
6barEFI1IB
else
6EFnot 6 B
6barEFnot 6barB
end ifD
else
6EF6B
6barEF6barB
end ifD
end %rocessB
end Be#aAioralB
arc#itecture dataCflo1 of srCff is
signal s1?s2DstdC logicB
begin
s1EFs nand cl!B
s2EFr nand cl!B
6EFs1 nand 6barB
6barEFs2 nand 6B
end dataCflo1B
arc#itecture structural of srff is
signal s1?s2DstdC logicB
com%onent nand2 is
%ort (a?bD in stdClogicB
c D out stdClogic)B

end com%onentB
begin
n1D nand2 %ort ma%(s?cl!?s1)B
n2D nand2 %ort ma%(r?cl!?s2)B
n&D nand2 %ort ma%(s1?6bar?6)B
n*D nand2 %ort ma%(s2?6?6bar)B
end structuralB
D + 1"I/ + 1"+/
/R+R!M,)
library =)))B
0se =))).S.DCL;G=C112*."llB
0se =))).S.DCL;G=C"$=.H."llB
0se =))).S.DCL;G=C03S=G3)D."llB
entity dff is
4ort (d D in stdClogicB
cl! D in stdClogicB
6 D in out stdClogicB
6bar D in out stdClogic)B
end dffB
arc#itecture Be#aAioral of dff is
begin
4rocess (d?cl!)
Begin
if (cl!IeAent and cl! FI1I)t#en
if(dFI9I)t#en
6EFI9IB
6barEFI1IB
else
6EFI1IB
6barEFI9IB
end ifD
else
6EF6B
6barEF 6barB
end ifD
end %rocessB
end Be#aAioralB
arc#itecture dataCflo1 of dCff is
signal s1?s2DstdC logicB
begin
s1EFd nand cl!B
s2EFnot d nand cl!B
6EFs1 nand 6barB
6barEFs2 nand 6B
end dataCflo1B
arc#itecture structural of dCff is
signal s1?s2?s&DstdC logicB
com%onent nand2 is
%ort (a?bD in stdClogicB
c D out stdClogic)B

end com%onentB
com%onent not1 is
%ort (aD in stdClogicB
c D out stdClogic)B

end com%onentB
begin
(1D not1 %ort ma%(d?s&)B
n1D nand2 %ort ma%(d?cl!?s1)B
n2D nand2 %ort ma%(s&?cl!?s2)B
n&D nand2 %ort ma%(s1?6bar?6)B
n*D nand2 %ort ma%(s2?6?6bar)B
end structuralB
84 + 1"I/ + 1"+/
/R+R!M,)
library =)))B
0se =))).S.DCL;G=C112*."llB
0se =))).S.DCL;G=C"$=.H."llB
0se =))).S.DCL;G=C03S=G3)D."llB
entity L!ff is
4ort (L D in stdClogicB
! D in stdClogicB
cl! D in stdClogicB
6 D in out stdClogicB
6bar D in out stdClogic)B
end L!ffB
arc#itecture Be#aAioral of L!ff is
begin
4rocess (L?cl!?!)
begin
if (cl!IeAent and cl! FI1I)t#en
if(LFI9Iand !FI9I)t#en
6EF6B
6barEF6barB
elsif(LFI9Iand !FI1I)t#en
6EFI9IB
6barEFI1IB
elsif(LFI1Iand !FI9I)t#en
6EFI1IB
6barEFI9IB
else
6EFnot 6 B
6barEFnot 6barB
end ifD
else
6EF6B
6barEF6barB
end ifD
end %rocessB
end Be#aAioralB
arc#itecture dataCflo1 of L!Cff is
signal s1?s2DstdC logicB
begin
s1EF! and cl! and 6B
s2EFL and cl! and 6barB
6EFs1 nor 6barB
6barEFs2 nor 6B
end dataCflo1B
arc#itecture structural of L!Cff is
signal s1?s2DstdC logicB
com%onent nor2 is
%ort (a?bD in stdClogicB
c D out stdClogic)B

end com%onentB
begin
com%onent and& is
%ort (a?b?cD in stdClogicB
d D out stdClogic)B

end com%onentB
begin
(1D and& %ort ma%(!?cl!?6?s1)B
(2D and& %ort ma%(L?cl!?6bar?s2)B
(&D nor2 %ort ma%(s1?6bar?6)B
(*D and2 %ort ma%(s2?6?6bar)B
end structuralB
T + 1"I/ + 1"+/
/R+R!M,)
library =)))B
0se =))).S.DCL;G=C112*."llB
0se =))).S.DCL;G=C"$=.H."llB
0se =))).S.DCL;G=C03S=G3)D."llB
entity tff is
4ort (t D in stdClogicB
cl! D in stdClogicB
6 D in out stdClogicB
6bar D in out stdClogic)B
end tffB
arc#itecture Be#aAioral of tff is
begin
4rocess (t?cl!?)
begin
if (cl!IeAent and cl! FI1I)t#en
if(tFI9I)t#en
6EF6B
6barEF6barB
else
6EFnot 6 B
6barEFnot 6barB
end ifD
else
6EF6B
6barEF6barB
end ifD
end %rocessB
end Be#aAioralB
arc#itecture dataCflo1 of tCff is
signal s1?s2DstdC logicB
begin
s1EFt and cl! and 6B
s2EFt and cl! and 6barB
6EFs1 nor 6barB
6barEFs2 nor 6B
end dataCflo1B
arc#itecture structural of tCff is
signal s1?s2 D stdC logicB
com%onent nor2 is
%ort (a?bD in stdClogicB
c D out stdClogic)B

end com%onentB
begin
com%onent and& is
%ort (a?b?cD in stdClogicB
d D out stdClogic)B

end com%onentB
begin
(1D and& %ort ma%(t?cl!?6?s1)B
(2D and& %ort ma%(t?cl!?6bar?s2)B
(&D nor2 %ort ma%(s1?6bar?6)B
(*D and2 %ort ma%(s2?6?6bar)B
end structuralB
DESIN !ND SIM3"!TI+N +1 C+3NTERS
E%. No , -9

!IM ,)
.o 1rite a VHDL ode for
$ing ounters
,o#nson ounters
0%+Do1n ounters
$i%%le ounters ("sync#ronous)
"nd Aerify t#e results.
$CD C+3NTER
/R+R!M,
library =)))B
0se =))).S.DCL;G=C112*."llB
0se =))).S.DCL;G=C"$=.H."llB
0se =))).S.DCL;G=C03S=G3)D."llB
entity modCnCcoun is
4ort (ceD in stdClogic B
cl!D in stdClogicB
6Din out stdClogic CAector (& do1nto 9))B
end modCnCcoun B
arc#itecture Be#aAioral of modCnCcoun is
begin
4rocess (ce?cl!)B
begin
if (ceIeAent and ce FI1I)t#en
6EFM9999MB
end ifD
if (cl!IeAent and cl! FI1I)t#en
if (ceFI1I)t#en
6EF6J1B
end ifB
if (6HFM1991M)t#en
6EFM9999MB
end ifB
end ifB
end %rocessB
end Be#aAioralB
$IN!R# 3/ D+:N C+3NTER
/R+R!M,)
library =)))B
0se =))).S.DCL;G=C112*."llB
0se =))).S.DCL;G=C"$=.H."llB
0se =))).S.DCL;G=C03S=G3)D."llB
entity binCu%Cdo1n is
4ort (u%D in stdClogic B
do1nD in stdClogicB
ceD in stdClogic B
cl!D in stdClogicB
6Din out stdClogic CAector (& do1nto 9))B
end binCu%Cdo1nB
arc#itecture Be#aAioral of binCu%Cdo1n is
begin
4rocess (u%? do1n? ce? cl!)B
begin
if (ceIeAent and ce FI1I)t#en
6EFM9999MB
end ifD
if (cl!IeAent and cl! FI1I)t#en
if (u%FI1I)t#en
6EF6J1B
else if(do1nFI1I)t#en
6EF6+1B
end ifB
end ifB
end %rocessB
end Be#aAioralB
!S#NC*R+N+3S C+3NTER
/R+R!M,)
library =)))B
0se =))).S.DCL;G=C112*."llB
0se =))).S.DCL;G=C"$=.H."llB
0se =))).S.DCL;G=C03S=G3)D."llB
entity asyCcount is
4ort (ceD in stdClogicB
cl!D in stdClogicB
nDin stdClogic CAector (& do1nto 9)B
6Din out stdClogic CAector (& do1nto 9))B
end asyCcountB
arc#itecture Be#aAioral of asyCcount is
begin
4rocess (ce? cl!?6)B
begin
if (ceIeAent and ce FI1I)t#en
6EFM9999MB
end ifD
if(6En)t#en
if (cl!IeAent and cl! FI1I)t#en
6(9)EFnot 6(9)B
if (6(9) FI1I)t#en
6(1)EFnot 6(1)B
if (6(1) FI1I)t#en
6(2)EFnot 6(2)B
if (6(2) FI1I)t#en
6(&)EFnot 6(&)B
end ifB
end ifB
end ifB
end ifB
else
6EFM9999MB
end ifB
end %rocessB
end Be#aAioralB
M+DE"IN +1 S*I1T REISTERS C+3NTERS
E%. No , -;

!IM ,)
.o 1rite VHDL 4rogram for reali>ing S#ift $egisters
Serial+in Serial+out
Serial in 4arallel out
4arallel in Serial out
4arallel in 4arallel out
"nd Aerify t#e results.
S*I1T REISTERS
Serial in serial o<t (SIS+=
/R+R!M,
library =)))B
0se =))).S.DCL;G=C112*."llB
0se =))).S.DCL;G=C"$=.H."llB
0se =))).S.DCL;G=C03S=G3)D."llB
)ntity siso is
4ort (siD in stdClogicB
cl!D in stdClogicB
soDin out stdClogic)B
end sisoB
arc#itecture structural of siso is
com%onent dCff is
4ort( d?cl!D in stdClogicB
6?6bar Din out stdClogic)B
end com%onentB
Signal a1? a2? a&? d1? d2? d&? d*DstdClogicB
begin
11DdCff %ort ma% (si? cl!? a1? d1)B
12DdCff %ort ma% (a1? cl!? a2? d2)B
1&DdCff %ort ma% (a2? cl!? a&? d&)B
1*DdCff %ort ma% (a&? cl!? so? d*)B
end structuralB
SI/+
/R+R!M,)
library =)))B
0se =))).S.DCL;G=C112*."llB
0se =))).S.DCL;G=C"$=.H."llB
0se =))).S.DCL;G=C03S=G3)D."llB
)ntity si%o is
4ort (siD in stdClogicB
cl!D in stdClogicB
%oDin out stdClogicCAector(& do1nto 9))B
end si%oB
arc#itecture structural of si%o is
signal dDstd ClogicC Aector(* do1nto 9)B
com%onent dCff
4ort (d?cl!D in stdClogicB
6?6bar Din out stdClogic)B
end com%onentB
begin
a1DdCff %ort ma% (si? cl!? %o(&)?d(&))B
a2DdCff %ort ma%( %o(&)? cl!? %o(2)?d(2))B
a&DdCff %ort ma% (%o(2)? cl!? %o(1)?d(1))B
a*DdCff %ort ma% (%o(1)? cl!? %o(9)?d(9))B
end structuralB
/IS+
/R+R!M,)
library =)))B
0se =))).S.DCL;G=C112*."llB
0se =))).S.DCL;G=C"$=.H."llB
0se =))).S.DCL;G=C03S=G3)D."llB
entity %iso is
4ort (%iD in stdClogic CAector (& do1nto 9)B
cD in stdClogicB
cl!D in stdClogicB
soDin out stdClogic)B
end %isoB
arc#itecture structural of %iso is
signal dDstdC logic Aector(& do1nto 9)B
signal 6Dstd Clogic Aector(& do1nto 1)B
signal aDstdC logic Aector(& do1nto 1)B
signal rDstd ClogicB
com%onent dCff is
4ort (d?cl!D in stdClogicB
6?6bar Din out stdClogic)B
end com%onentB
com%onent aoi is
4ort (a?b?c?dD in stdClogicB
cD out stdClogic)B
end com%onentB
begin
a1Daio %ort ma% (6 (&)?r?c?%i(2)a(&))B
a2Daio %ort ma%( 6 (2)?r?c?%i(1)a(2))B
a&Daio %ort ma% (6 (1)?r?c?%i(9)a(1))B
11DdCff %ort ma%( %i(&)? cl!? 6(&)?d(&))B
12DdCff %ort ma%(a(&)? cl!? 6(2)?d(2))B
1&DdCff %ort ma%(a(2)? cl!? 6(1)?d(1))B
1*DdCff %ort ma%(a(1)? cl!? so?d(9))B
end structuralB
/I/+
/R+R!M,)
library =)))B
0se =))).S.DCL;G=C112*."llB
0se =))).S.DCL;G=C"$=.H."llB
0se =))).S.DCL;G=C03S=G3)D."llB
entity %i%o is
4ort (%iD in stdClogic CAector (& do1nto 9)B
cl!D in stdClogicB
%oDin out stdClogic CAector (& do1nto 9))B
end %i%oB
arc#itecture structural of %i%o is
signal dDstdC logic Aector(* do1nto 9)B
com%onent dCff is
4ort (d?cl!D in stdClogicB
6?6bar Din out stdClogic)B
end com%onentB
begin
11DdCff %ort ma%( %i(&)? cl!? %o(&)?d(&))B
12DdCff %ort ma%( %i(2)? cl!? %o(2)?d(2))B
1&DdCff %ort ma%( %i(1)? cl!? %o(1)?d(1))B
1*DdCff %ort ma%( %i(9)? cl!? %o(9)?d(9))B
end structuralB

Serial in serial o<t (SIS+=
Serial In&<t
Clk

Serial +<t
Serial in /arallel o<t (SI/+=

Serial In&<t
Clk

/arallel +<t
>(n)2= >(n)5= >(-= >(n).=
>(n)2= >(n)5= >(-= >(n).=
/arallel in o<t Serial (/IS+=
/arallel In
Clk

Serial +<t
/arallel in /arallel o<t(/I/+=

/arallel In
Clk
"oa?
/arallel +<t
SIS+ /I/+
SIN C"4 S+3T
. 3
- .
- -
. -
. .
. .
- .
IN/3T +3T/3T
SIN C"4
>- >. >2 >5
. 3 3 3 3
- . 3 3 3
- - . 3 3
. - - . 3
. . - - .
. . . - -
>(n)2= >(n)5= >(-= >(n).=
>(n)2= >(n)5= >(-= >(n).=
/IS+
/I/+
M+D)N $CD Co<nter

<9
<1
l!
<2
<&
IN/3T
+3T/3T
"+!D C"4
IN- IN. IN. IN. S+3T
. - - . 3
0 . . - - .
0 . . . - -
0 . . . . -
0 . . . . .
IN/3T
+3T/3T
"+!D C"4
.- .. I2 I5 >- >. >2 >5
0 . - - . 3 3 3 3
0 . - - . . - - .
0 . . - . . - - .
- . - - . . - .
0 - . - - - . - -
IN/3T +3T/3T
SIN C"4
>- >. >2 >5
. 3 3 3 3
- . 3 3 3
- - . 3 3
. - - . 3
. . - - .
. . . - -
';D+3
BD
ounter
$IN!R# 3/ D+:N C+3NTER
<9
04
D3 <1
l! <2
<&
!S#NC*R+N+3S C+3NTER
<9
l!
<1
<9
<2
<1
<&
<2
C"R
B=3"$N
04
D;:3
;03.)$
"sync#ronous
ounter
M+DE""IN +1 M3"TI/"IERS
E%. No , -6

!IM ,)
.o 1rite VHDL 4rogram for reali>ing multi%liers li!e "rray
'ulti%lier and Aerify t#e results.
/R+R!M,)
library =)))B
0se =))).S.DCL;G=C112*."llB
0se =))).S.DCL;G=C"$=.H."llB
0se =))).S.DCL;G=C03S=G3)D."llB
entity unsignCmul is
4ort ((D in stdClogic CAector(& do1nto 9)B
y D in stdClogic CAector(& do1nto 9)B
l D in stdClogicB
% D inout stdClogic CAector(5 do1nto 9)B
end unsignCmulB
arc#itecture Be#aAioral of unsignCmul is
signal m D stdC logicC Aector(5 do1nto 9)B
signal i D integerB
begin
%rocessor((?y?i)
begin
if (lIeAent and l FI1I)t#en
6EFM99999999MB
mEFM9999MO(B
iEF9B
else
6barEF6barB
if(iE*)t#en
if(y(i)FI1I)t#en
6EF%JmB
else
%EF%B
iEFiJ1 after /9 %sB
mEFm(2 do1nto 9)OI9IB
end ifB
end ifB
end %rocessB
end Be#aAioralB
R!M
E%. No , -@

!IM ,)
.o 1rite VHDL 4rogram for $"' and Aerify t#e results.
/R+R!M,)
library ieeeB
use ieee.stdClogicC112*.allB
entity ram is
%ort(dinDin stdClogicCAector(5 do1nto 9)B
rd?1r?cl!Din stdClogicB
locnDin integer range 9 to 5B
doutDout stdClogicCAector(5 do1nto 9))B
end ramB
arc#itecture be#aA of ram is
ty%e mem is array(integer range 9 to 5) of stdClogicCAector(5 do1nto 9)B
signal sramDmemB
begin
%rocess(cl!?rd?1r)
begin
if((rd and 1r)PFG1G)t#en
if(cl!GeAent and cl!FG1G)t#en
if(rdFG1G)t#en
doutEFsram(locn)B
else if(1rFG1G)t#en
sram(locn)EFdinB
end ifB
end ifB
end ifB
end ifB
end %rocessB
end be#aAB
ST!C4 !ND >3E3E IM/"EMENT!TI+NS
E%. No , .-

!IM ,)
.o 1rite VHDL 4rogram for Stac! and <ueue =m%lementations
and Aerify t#e results.
/R+R!M,)
library ieeeB
use ieee.stdClogicC112*.allB
entity stac! is
%ort ( rd?1r?cl!?clrDin stdClogicB
dataD inout stdClogicCAector(5 do1nto 9)B
fulDout stdClogic)B
end stac!B
arc#itecture 6ue of stac! is
ty%e store is array(natural range EH)of stdClogicCAector(5 do1nto 9)B
signal addressD integer range 9 to 1/B
signal memoryDstore(9 to 1/)B
begin
%rocess (data ?rd ?1r?clr?cl!)
begin
if clrFG1G t#en
memoryEF(ot#ersFH(ot#ersFHG9G))B
fulEFG9GB
addressEF9B
elsif(cl!FG1Gand cl!GeAent)t#en
if addressF1/ t#en
fulEFG1GB
else
memory(address)EFdataB
addressEFaddressJ1B
end ifB
elsif (rdFG1G)t#en
if (addressF9)t#en
fulEFG9GB
else
dataEFmemory(address)B
addressEFaddress+1B
end ifB
end ifB
end %rocessB
end 6ueB